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@@ -13,6 +13,10 @@
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#include "sh_pfc.h"
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+/*
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+ * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
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+ * which case they support both 3.3V and 1.8V signalling.
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+ */
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#define CPU_ALL_PORT(fn, sfx) \
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PORT_GP_32(0, fn, sfx), \
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PORT_GP_26(1, fn, sfx), \
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@@ -20,7 +24,15 @@
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PORT_GP_32(3, fn, sfx), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_32(5, fn, sfx), \
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- PORT_GP_32(6, fn, sfx), \
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+ PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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+ PORT_GP_1(6, 24, fn, sfx), \
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+ PORT_GP_1(6, 25, fn, sfx), \
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+ PORT_GP_1(6, 26, fn, sfx), \
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+ PORT_GP_1(6, 27, fn, sfx), \
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+ PORT_GP_1(6, 28, fn, sfx), \
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+ PORT_GP_1(6, 29, fn, sfx), \
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+ PORT_GP_1(6, 30, fn, sfx), \
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+ PORT_GP_1(6, 31, fn, sfx), \
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PORT_GP_26(7, fn, sfx)
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enum {
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@@ -6404,9 +6416,24 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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{ },
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};
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+static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
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+{
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+ if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
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+ return -EINVAL;
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+
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+ *pocctrl = 0xe606008c;
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+
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+ return 31 - (pin & 0x1f);
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+}
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+
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+static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
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+ .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
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+};
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+
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#ifdef CONFIG_PINCTRL_PFC_R8A7791
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const struct sh_pfc_soc_info r8a7791_pinmux_info = {
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.name = "r8a77910_pfc",
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+ .ops = &r8a7791_pinmux_ops,
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.unlock_reg = 0xe6060000, /* PMMR */
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.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
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