|
@@ -127,6 +127,10 @@ ENDPROC(cpu_resume_after_mmu)
|
|
|
.align
|
|
|
ENTRY(cpu_resume)
|
|
|
ARM_BE8(setend be) @ ensure we are in BE mode
|
|
|
+#ifdef CONFIG_ARM_VIRT_EXT
|
|
|
+ bl __hyp_stub_install_secondary
|
|
|
+#endif
|
|
|
+ safe_svcmode_maskall r1
|
|
|
mov r1, #0
|
|
|
ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
|
|
|
ALT_UP_B(1f)
|
|
@@ -144,7 +148,6 @@ ARM_BE8(setend be) @ ensure we are in BE mode
|
|
|
ldr r0, [r0, #SLEEP_SAVE_SP_PHYS]
|
|
|
ldr r0, [r0, r1, lsl #2]
|
|
|
|
|
|
- setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
|
|
|
@ load phys pgd, stack, resume fn
|
|
|
ARM( ldmia r0!, {r1, sp, pc} )
|
|
|
THUMB( ldmia r0!, {r1, r2, r3} )
|