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@@ -182,6 +182,14 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
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vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
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DPIO_OPCODE_REG_READ, reg, &val);
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+
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+ /*
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+ * FIXME: There might be some registers where all 1's is a valid value,
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+ * so ideally we should check the register offset instead...
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+ */
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+ WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
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+ pipe_name(pipe), reg, val);
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+
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return val;
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}
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