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@@ -62,6 +62,30 @@
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ranges = <0 0xf7000000 0x1000000>;
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interrupt-parent = <&gic>;
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+ sdhci0: sdhci@ab0000 {
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+ compatible = "mrvl,pxav3-mmc";
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+ reg = <0xab0000 0x200>;
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+ clocks = <&chip CLKID_SDIO1XIN>;
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+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ sdhci1: sdhci@ab0800 {
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+ compatible = "mrvl,pxav3-mmc";
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+ reg = <0xab0800 0x200>;
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+ clocks = <&chip CLKID_SDIO1XIN>;
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+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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+ status = "disabled";
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+ };
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+
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+ sdhci2: sdhci@ab1000 {
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+ compatible = "mrvl,pxav3-mmc";
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+ reg = <0xab1000 0x200>;
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+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&chip CLKID_SDIO1XIN>;
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+ status = "disabled";
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+ };
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+
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l2: l2-cache-controller@ac0000 {
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compatible = "arm,pl310-cache";
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reg = <0xac0000 0x1000>;
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