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@@ -79,7 +79,7 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
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{
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long mfi, mfn, mfd, pdf, ref_clk;
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unsigned long dbl;
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- s64 temp;
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+ u64 temp;
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dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
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@@ -98,8 +98,9 @@ static unsigned long __clk_pllv2_recalc_rate(unsigned long parent_rate,
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temp = (u64) ref_clk * abs(mfn);
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do_div(temp, mfd + 1);
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if (mfn < 0)
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- temp = -temp;
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- temp = (ref_clk * mfi) + temp;
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+ temp = (ref_clk * mfi) - temp;
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+ else
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+ temp = (ref_clk * mfi) + temp;
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return temp;
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}
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@@ -126,7 +127,7 @@ static int __clk_pllv2_set_rate(unsigned long rate, unsigned long parent_rate,
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{
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u32 reg;
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long mfi, pdf, mfn, mfd = 999999;
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- s64 temp64;
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+ u64 temp64;
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unsigned long quad_parent_rate;
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quad_parent_rate = 4 * parent_rate;
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