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@@ -0,0 +1,763 @@
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+/*
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+ * MediaTek xHCI Host Controller Driver
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+ *
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+ * Copyright (c) 2015 MediaTek Inc.
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+ * Author:
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+ * Chunfeng Yun <chunfeng.yun@mediatek.com>
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+ *
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+ * This software is licensed under the terms of the GNU General Public
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+ * License version 2, as published by the Free Software Foundation, and
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+ * may be copied, distributed, and modified under those terms.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/iopoll.h>
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+#include <linux/kernel.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/phy/phy.h>
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+#include <linux/platform_device.h>
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+#include <linux/pm_runtime.h>
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+#include <linux/regmap.h>
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+#include <linux/regulator/consumer.h>
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+
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+#include "xhci.h"
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+#include "xhci-mtk.h"
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+
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+/* ip_pw_ctrl0 register */
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+#define CTRL0_IP_SW_RST BIT(0)
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+
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+/* ip_pw_ctrl1 register */
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+#define CTRL1_IP_HOST_PDN BIT(0)
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+
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+/* ip_pw_ctrl2 register */
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+#define CTRL2_IP_DEV_PDN BIT(0)
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+
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+/* ip_pw_sts1 register */
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+#define STS1_IP_SLEEP_STS BIT(30)
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+#define STS1_XHCI_RST BIT(11)
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+#define STS1_SYS125_RST BIT(10)
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+#define STS1_REF_RST BIT(8)
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+#define STS1_SYSPLL_STABLE BIT(0)
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+
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+/* ip_xhci_cap register */
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+#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
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+#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
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+
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+/* u3_ctrl_p register */
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+#define CTRL_U3_PORT_HOST_SEL BIT(2)
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+#define CTRL_U3_PORT_PDN BIT(1)
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+#define CTRL_U3_PORT_DIS BIT(0)
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+
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+/* u2_ctrl_p register */
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+#define CTRL_U2_PORT_HOST_SEL BIT(2)
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+#define CTRL_U2_PORT_PDN BIT(1)
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+#define CTRL_U2_PORT_DIS BIT(0)
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+
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+/* u2_phy_pll register */
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+#define CTRL_U2_FORCE_PLL_STB BIT(28)
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+
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+#define PERI_WK_CTRL0 0x400
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+#define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
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+#define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
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+#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
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+#define UWK_CTL1_1P_LS_E BIT(0)
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+
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+#define PERI_WK_CTRL1 0x404
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+#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
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+#define UWK_CTL1_IS_E BIT(25)
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+#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
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+#define UWK_CTL1_0P_LS_E BIT(20)
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+#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
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+#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
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+#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
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+#define UWK_CTL1_0P_LS_P BIT(7)
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+#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
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+
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+enum ssusb_wakeup_src {
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+ SSUSB_WK_IP_SLEEP = 1,
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+ SSUSB_WK_LINE_STATE = 2,
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+};
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+
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+static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
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+{
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+ struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
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+ u32 value, check_val;
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+ int ret;
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+ int i;
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+
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+ /* power on host ip */
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+ value = readl(&ippc->ip_pw_ctr1);
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+ value &= ~CTRL1_IP_HOST_PDN;
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+ writel(value, &ippc->ip_pw_ctr1);
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+
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+ /* power on and enable all u3 ports */
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+ for (i = 0; i < mtk->num_u3_ports; i++) {
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+ value = readl(&ippc->u3_ctrl_p[i]);
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+ value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
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+ value |= CTRL_U3_PORT_HOST_SEL;
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+ writel(value, &ippc->u3_ctrl_p[i]);
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+ }
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+
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+ /* power on and enable all u2 ports */
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+ for (i = 0; i < mtk->num_u2_ports; i++) {
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+ value = readl(&ippc->u2_ctrl_p[i]);
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+ value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
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+ value |= CTRL_U2_PORT_HOST_SEL;
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+ writel(value, &ippc->u2_ctrl_p[i]);
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+ }
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+
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+ /*
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+ * wait for clocks to be stable, and clock domains reset to
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+ * be inactive after power on and enable ports
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+ */
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+ check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
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+ STS1_SYS125_RST | STS1_XHCI_RST;
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+
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+ ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
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+ (check_val == (value & check_val)), 100, 20000);
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+ if (ret) {
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+ dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
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+ return ret;
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+ }
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+
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+ return 0;
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+}
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+
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+static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
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+{
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+ struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
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+ u32 value;
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+ int ret;
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+ int i;
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+
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+ /* power down all u3 ports */
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+ for (i = 0; i < mtk->num_u3_ports; i++) {
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+ value = readl(&ippc->u3_ctrl_p[i]);
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+ value |= CTRL_U3_PORT_PDN;
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+ writel(value, &ippc->u3_ctrl_p[i]);
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+ }
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+
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+ /* power down all u2 ports */
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+ for (i = 0; i < mtk->num_u2_ports; i++) {
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+ value = readl(&ippc->u2_ctrl_p[i]);
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+ value |= CTRL_U2_PORT_PDN;
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+ writel(value, &ippc->u2_ctrl_p[i]);
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+ }
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+
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+ /* power down host ip */
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+ value = readl(&ippc->ip_pw_ctr1);
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+ value |= CTRL1_IP_HOST_PDN;
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+ writel(value, &ippc->ip_pw_ctr1);
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+
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+ /* wait for host ip to sleep */
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+ ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
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+ (value & STS1_IP_SLEEP_STS), 100, 100000);
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+ if (ret) {
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+ dev_err(mtk->dev, "ip sleep failed!!!\n");
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+ return ret;
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+ }
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+ return 0;
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+}
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+
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+static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
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+{
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+ struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
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+ u32 value;
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+
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+ /* reset whole ip */
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+ value = readl(&ippc->ip_pw_ctr0);
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+ value |= CTRL0_IP_SW_RST;
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+ writel(value, &ippc->ip_pw_ctr0);
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+ udelay(1);
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+ value = readl(&ippc->ip_pw_ctr0);
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+ value &= ~CTRL0_IP_SW_RST;
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+ writel(value, &ippc->ip_pw_ctr0);
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+
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+ /*
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+ * device ip is default power-on in fact
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+ * power down device ip, otherwise ip-sleep will fail
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+ */
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+ value = readl(&ippc->ip_pw_ctr2);
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+ value |= CTRL2_IP_DEV_PDN;
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+ writel(value, &ippc->ip_pw_ctr2);
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+
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+ value = readl(&ippc->ip_xhci_cap);
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+ mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
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+ mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
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+ dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
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+ mtk->num_u2_ports, mtk->num_u3_ports);
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+
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+ return xhci_mtk_host_enable(mtk);
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+}
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+
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+static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
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+{
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+ int ret;
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+
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+ ret = clk_prepare_enable(mtk->sys_clk);
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+ if (ret) {
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+ dev_err(mtk->dev, "failed to enable sys_clk\n");
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+ goto sys_clk_err;
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+ }
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+
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+ if (mtk->wakeup_src) {
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+ ret = clk_prepare_enable(mtk->wk_deb_p0);
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+ if (ret) {
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+ dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
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+ goto usb_p0_err;
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+ }
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+
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+ ret = clk_prepare_enable(mtk->wk_deb_p1);
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+ if (ret) {
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+ dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
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+ goto usb_p1_err;
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+ }
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+ }
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+ return 0;
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+
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+usb_p1_err:
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+ clk_disable_unprepare(mtk->wk_deb_p0);
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+usb_p0_err:
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+ clk_disable_unprepare(mtk->sys_clk);
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+sys_clk_err:
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+ return -EINVAL;
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+}
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+
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+static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
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+{
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+ if (mtk->wakeup_src) {
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+ clk_disable_unprepare(mtk->wk_deb_p1);
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+ clk_disable_unprepare(mtk->wk_deb_p0);
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+ }
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+ clk_disable_unprepare(mtk->sys_clk);
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+}
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+
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+/* only clocks can be turn off for ip-sleep wakeup mode */
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+static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
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+{
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+ u32 tmp;
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+ struct regmap *pericfg = mtk->pericfg;
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+
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+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
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+ tmp &= ~UWK_CTL1_IS_P;
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+ tmp &= ~(UWK_CTL1_IS_C(0xf));
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+ tmp |= UWK_CTL1_IS_C(0x8);
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+ regmap_write(pericfg, PERI_WK_CTRL1, tmp);
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+ regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
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+
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+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
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+ dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
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+ __func__, tmp);
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+}
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+
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+static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
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+{
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+ u32 tmp;
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+
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+ regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
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+ tmp &= ~UWK_CTL1_IS_E;
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+ regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
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+}
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+
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+/*
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+* for line-state wakeup mode, phy's power should not power-down
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+* and only support cable plug in/out
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+*/
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+static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
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+{
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+ u32 tmp;
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+ struct regmap *pericfg = mtk->pericfg;
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+
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+ /* line-state of u2-port0 */
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+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
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+ tmp &= ~UWK_CTL1_0P_LS_P;
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+ tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
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+ tmp |= UWK_CTL1_0P_LS_C(0x8);
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+ regmap_write(pericfg, PERI_WK_CTRL1, tmp);
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+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
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+ regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
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+
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+ /* line-state of u2-port1 */
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+ regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
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+ tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
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+ tmp |= UWK_CTL1_1P_LS_C(0x8);
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+ regmap_write(pericfg, PERI_WK_CTRL0, tmp);
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+ regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
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+}
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+
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+static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
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+{
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+ u32 tmp;
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+ struct regmap *pericfg = mtk->pericfg;
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+
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+ /* line-state of u2-port0 */
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+ regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
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+ tmp &= ~UWK_CTL1_0P_LS_E;
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+ regmap_write(pericfg, PERI_WK_CTRL1, tmp);
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+
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+ /* line-state of u2-port1 */
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+ regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
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+ tmp &= ~UWK_CTL1_1P_LS_E;
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+ regmap_write(pericfg, PERI_WK_CTRL0, tmp);
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+}
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+
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+static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
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+{
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+ if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
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+ usb_wakeup_ip_sleep_en(mtk);
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+ else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
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+ usb_wakeup_line_state_en(mtk);
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+}
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+
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+static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
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+{
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+ if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
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+ usb_wakeup_ip_sleep_dis(mtk);
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+ else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
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+ usb_wakeup_line_state_dis(mtk);
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+}
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+
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+static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
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+ struct device_node *dn)
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+{
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+ struct device *dev = mtk->dev;
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+
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+ /*
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+ * wakeup function is optional, so it is not an error if this property
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+ * does not exist, and in such case, no need to get relative
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+ * properties anymore.
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+ */
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+ of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
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+ if (!mtk->wakeup_src)
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+ return 0;
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+
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+ mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
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+ if (IS_ERR(mtk->wk_deb_p0)) {
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+ dev_err(dev, "fail to get wakeup_deb_p0\n");
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+ return PTR_ERR(mtk->wk_deb_p0);
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+ }
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+
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+ mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
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+ if (IS_ERR(mtk->wk_deb_p1)) {
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+ dev_err(dev, "fail to get wakeup_deb_p1\n");
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+ return PTR_ERR(mtk->wk_deb_p1);
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+ }
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+
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+ mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
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+ "mediatek,syscon-wakeup");
|
|
|
+ if (IS_ERR(mtk->pericfg)) {
|
|
|
+ dev_err(dev, "fail to get pericfg regs\n");
|
|
|
+ return PTR_ERR(mtk->pericfg);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_setup(struct usb_hcd *hcd);
|
|
|
+static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
|
|
|
+ .extra_priv_size = sizeof(struct xhci_hcd),
|
|
|
+ .reset = xhci_mtk_setup,
|
|
|
+};
|
|
|
+
|
|
|
+static struct hc_driver __read_mostly xhci_mtk_hc_driver;
|
|
|
+
|
|
|
+static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ for (i = 0; i < mtk->num_phys; i++) {
|
|
|
+ ret = phy_init(mtk->phys[i]);
|
|
|
+ if (ret)
|
|
|
+ goto exit_phy;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+
|
|
|
+exit_phy:
|
|
|
+ for (; i > 0; i--)
|
|
|
+ phy_exit(mtk->phys[i - 1]);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ for (i = 0; i < mtk->num_phys; i++)
|
|
|
+ phy_exit(mtk->phys[i]);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ for (i = 0; i < mtk->num_phys; i++) {
|
|
|
+ ret = phy_power_on(mtk->phys[i]);
|
|
|
+ if (ret)
|
|
|
+ goto power_off_phy;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+
|
|
|
+power_off_phy:
|
|
|
+ for (; i > 0; i--)
|
|
|
+ phy_power_off(mtk->phys[i - 1]);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
|
|
|
+{
|
|
|
+ unsigned int i;
|
|
|
+
|
|
|
+ for (i = 0; i < mtk->num_phys; i++)
|
|
|
+ phy_power_off(mtk->phys[i]);
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
|
|
|
+{
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = regulator_enable(mtk->vbus);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(mtk->dev, "failed to enable vbus\n");
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = regulator_enable(mtk->vusb33);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(mtk->dev, "failed to enable vusb33\n");
|
|
|
+ regulator_disable(mtk->vbus);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
|
|
|
+{
|
|
|
+ regulator_disable(mtk->vbus);
|
|
|
+ regulator_disable(mtk->vusb33);
|
|
|
+}
|
|
|
+
|
|
|
+static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
|
|
|
+{
|
|
|
+ struct usb_hcd *hcd = xhci_to_hcd(xhci);
|
|
|
+ struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * As of now platform drivers don't provide MSI support so we ensure
|
|
|
+ * here that the generic code does not try to make a pci_dev from our
|
|
|
+ * dev struct in order to setup MSI
|
|
|
+ */
|
|
|
+ xhci->quirks |= XHCI_PLAT;
|
|
|
+ xhci->quirks |= XHCI_MTK_HOST;
|
|
|
+ /*
|
|
|
+ * MTK host controller gives a spurious successful event after a
|
|
|
+ * short transfer. Ignore it.
|
|
|
+ */
|
|
|
+ xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
|
|
|
+ if (mtk->lpm_support)
|
|
|
+ xhci->quirks |= XHCI_LPM_SUPPORT;
|
|
|
+}
|
|
|
+
|
|
|
+/* called during probe() after chip reset completes */
|
|
|
+static int xhci_mtk_setup(struct usb_hcd *hcd)
|
|
|
+{
|
|
|
+ struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ if (usb_hcd_is_primary_hcd(hcd)) {
|
|
|
+ ret = xhci_mtk_ssusb_config(mtk);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ ret = xhci_mtk_sch_init(mtk);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ return xhci_gen_setup(hcd, xhci_mtk_quirks);
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct device_node *node = dev->of_node;
|
|
|
+ struct xhci_hcd_mtk *mtk;
|
|
|
+ const struct hc_driver *driver;
|
|
|
+ struct xhci_hcd *xhci;
|
|
|
+ struct resource *res;
|
|
|
+ struct usb_hcd *hcd;
|
|
|
+ struct phy *phy;
|
|
|
+ int phy_num;
|
|
|
+ int ret = -ENODEV;
|
|
|
+ int irq;
|
|
|
+
|
|
|
+ if (usb_disabled())
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ driver = &xhci_mtk_hc_driver;
|
|
|
+ mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
|
|
|
+ if (!mtk)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ mtk->dev = dev;
|
|
|
+ mtk->vbus = devm_regulator_get(dev, "vbus");
|
|
|
+ if (IS_ERR(mtk->vbus)) {
|
|
|
+ dev_err(dev, "fail to get vbus\n");
|
|
|
+ return PTR_ERR(mtk->vbus);
|
|
|
+ }
|
|
|
+
|
|
|
+ mtk->vusb33 = devm_regulator_get(dev, "vusb33");
|
|
|
+ if (IS_ERR(mtk->vusb33)) {
|
|
|
+ dev_err(dev, "fail to get vusb33\n");
|
|
|
+ return PTR_ERR(mtk->vusb33);
|
|
|
+ }
|
|
|
+
|
|
|
+ mtk->sys_clk = devm_clk_get(dev, "sys_ck");
|
|
|
+ if (IS_ERR(mtk->sys_clk)) {
|
|
|
+ dev_err(dev, "fail to get sys_ck\n");
|
|
|
+ return PTR_ERR(mtk->sys_clk);
|
|
|
+ }
|
|
|
+
|
|
|
+ mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
|
|
|
+
|
|
|
+ ret = usb_wakeup_of_property_parse(mtk, node);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ mtk->num_phys = of_count_phandle_with_args(node,
|
|
|
+ "phys", "#phy-cells");
|
|
|
+ if (mtk->num_phys > 0) {
|
|
|
+ mtk->phys = devm_kcalloc(dev, mtk->num_phys,
|
|
|
+ sizeof(*mtk->phys), GFP_KERNEL);
|
|
|
+ if (!mtk->phys)
|
|
|
+ return -ENOMEM;
|
|
|
+ } else {
|
|
|
+ mtk->num_phys = 0;
|
|
|
+ }
|
|
|
+ pm_runtime_enable(dev);
|
|
|
+ pm_runtime_get_sync(dev);
|
|
|
+ device_enable_async_suspend(dev);
|
|
|
+
|
|
|
+ ret = xhci_mtk_ldos_enable(mtk);
|
|
|
+ if (ret)
|
|
|
+ goto disable_pm;
|
|
|
+
|
|
|
+ ret = xhci_mtk_clks_enable(mtk);
|
|
|
+ if (ret)
|
|
|
+ goto disable_ldos;
|
|
|
+
|
|
|
+ irq = platform_get_irq(pdev, 0);
|
|
|
+ if (irq < 0)
|
|
|
+ goto disable_clk;
|
|
|
+
|
|
|
+ /* Initialize dma_mask and coherent_dma_mask to 32-bits */
|
|
|
+ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
|
|
|
+ if (ret)
|
|
|
+ goto disable_clk;
|
|
|
+
|
|
|
+ if (!dev->dma_mask)
|
|
|
+ dev->dma_mask = &dev->coherent_dma_mask;
|
|
|
+ else
|
|
|
+ dma_set_mask(dev, DMA_BIT_MASK(32));
|
|
|
+
|
|
|
+ hcd = usb_create_hcd(driver, dev, dev_name(dev));
|
|
|
+ if (!hcd) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto disable_clk;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * USB 2.0 roothub is stored in the platform_device.
|
|
|
+ * Swap it with mtk HCD.
|
|
|
+ */
|
|
|
+ mtk->hcd = platform_get_drvdata(pdev);
|
|
|
+ platform_set_drvdata(pdev, mtk);
|
|
|
+
|
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ hcd->regs = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(hcd->regs)) {
|
|
|
+ ret = PTR_ERR(hcd->regs);
|
|
|
+ goto put_usb2_hcd;
|
|
|
+ }
|
|
|
+ hcd->rsrc_start = res->start;
|
|
|
+ hcd->rsrc_len = resource_size(res);
|
|
|
+
|
|
|
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
|
|
+ mtk->ippc_regs = devm_ioremap_resource(dev, res);
|
|
|
+ if (IS_ERR(mtk->ippc_regs)) {
|
|
|
+ ret = PTR_ERR(mtk->ippc_regs);
|
|
|
+ goto put_usb2_hcd;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
|
|
|
+ phy = devm_of_phy_get_by_index(dev, node, phy_num);
|
|
|
+ if (IS_ERR(phy)) {
|
|
|
+ ret = PTR_ERR(phy);
|
|
|
+ goto put_usb2_hcd;
|
|
|
+ }
|
|
|
+ mtk->phys[phy_num] = phy;
|
|
|
+ }
|
|
|
+
|
|
|
+ ret = xhci_mtk_phy_init(mtk);
|
|
|
+ if (ret)
|
|
|
+ goto put_usb2_hcd;
|
|
|
+
|
|
|
+ ret = xhci_mtk_phy_power_on(mtk);
|
|
|
+ if (ret)
|
|
|
+ goto exit_phys;
|
|
|
+
|
|
|
+ device_init_wakeup(dev, true);
|
|
|
+
|
|
|
+ xhci = hcd_to_xhci(hcd);
|
|
|
+ xhci->main_hcd = hcd;
|
|
|
+ xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
|
|
|
+ dev_name(dev), hcd);
|
|
|
+ if (!xhci->shared_hcd) {
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto power_off_phys;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
|
|
|
+ xhci->shared_hcd->can_do_streams = 1;
|
|
|
+
|
|
|
+ ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
|
|
|
+ if (ret)
|
|
|
+ goto put_usb3_hcd;
|
|
|
+
|
|
|
+ ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
|
|
|
+ if (ret)
|
|
|
+ goto dealloc_usb2_hcd;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+dealloc_usb2_hcd:
|
|
|
+ usb_remove_hcd(hcd);
|
|
|
+
|
|
|
+put_usb3_hcd:
|
|
|
+ xhci_mtk_sch_exit(mtk);
|
|
|
+ usb_put_hcd(xhci->shared_hcd);
|
|
|
+
|
|
|
+power_off_phys:
|
|
|
+ xhci_mtk_phy_power_off(mtk);
|
|
|
+ device_init_wakeup(dev, false);
|
|
|
+
|
|
|
+exit_phys:
|
|
|
+ xhci_mtk_phy_exit(mtk);
|
|
|
+
|
|
|
+put_usb2_hcd:
|
|
|
+ usb_put_hcd(hcd);
|
|
|
+
|
|
|
+disable_clk:
|
|
|
+ xhci_mtk_clks_disable(mtk);
|
|
|
+
|
|
|
+disable_ldos:
|
|
|
+ xhci_mtk_ldos_disable(mtk);
|
|
|
+
|
|
|
+disable_pm:
|
|
|
+ pm_runtime_put_sync(dev);
|
|
|
+ pm_runtime_disable(dev);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_remove(struct platform_device *dev)
|
|
|
+{
|
|
|
+ struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
|
|
|
+ struct usb_hcd *hcd = mtk->hcd;
|
|
|
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
+
|
|
|
+ usb_remove_hcd(xhci->shared_hcd);
|
|
|
+ xhci_mtk_phy_power_off(mtk);
|
|
|
+ xhci_mtk_phy_exit(mtk);
|
|
|
+ device_init_wakeup(&dev->dev, false);
|
|
|
+
|
|
|
+ usb_remove_hcd(hcd);
|
|
|
+ usb_put_hcd(xhci->shared_hcd);
|
|
|
+ usb_put_hcd(hcd);
|
|
|
+ xhci_mtk_sch_exit(mtk);
|
|
|
+ xhci_mtk_clks_disable(mtk);
|
|
|
+ xhci_mtk_ldos_disable(mtk);
|
|
|
+ pm_runtime_put_sync(&dev->dev);
|
|
|
+ pm_runtime_disable(&dev->dev);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
|
+static int xhci_mtk_suspend(struct device *dev)
|
|
|
+{
|
|
|
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
|
|
|
+
|
|
|
+ xhci_mtk_host_disable(mtk);
|
|
|
+ xhci_mtk_phy_power_off(mtk);
|
|
|
+ xhci_mtk_clks_disable(mtk);
|
|
|
+ usb_wakeup_enable(mtk);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int xhci_mtk_resume(struct device *dev)
|
|
|
+{
|
|
|
+ struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
|
|
|
+
|
|
|
+ usb_wakeup_disable(mtk);
|
|
|
+ xhci_mtk_clks_enable(mtk);
|
|
|
+ xhci_mtk_phy_power_on(mtk);
|
|
|
+ xhci_mtk_host_enable(mtk);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct dev_pm_ops xhci_mtk_pm_ops = {
|
|
|
+ SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
|
|
|
+};
|
|
|
+#define DEV_PM_OPS (&xhci_mtk_pm_ops)
|
|
|
+#else
|
|
|
+#define DEV_PM_OPS NULL
|
|
|
+#endif /* CONFIG_PM */
|
|
|
+
|
|
|
+#ifdef CONFIG_OF
|
|
|
+static const struct of_device_id mtk_xhci_of_match[] = {
|
|
|
+ { .compatible = "mediatek,mt8173-xhci"},
|
|
|
+ { },
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
|
|
|
+#endif
|
|
|
+
|
|
|
+static struct platform_driver mtk_xhci_driver = {
|
|
|
+ .probe = xhci_mtk_probe,
|
|
|
+ .remove = xhci_mtk_remove,
|
|
|
+ .driver = {
|
|
|
+ .name = "xhci-mtk",
|
|
|
+ .pm = DEV_PM_OPS,
|
|
|
+ .of_match_table = of_match_ptr(mtk_xhci_of_match),
|
|
|
+ },
|
|
|
+};
|
|
|
+MODULE_ALIAS("platform:xhci-mtk");
|
|
|
+
|
|
|
+static int __init xhci_mtk_init(void)
|
|
|
+{
|
|
|
+ xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
|
|
|
+ return platform_driver_register(&mtk_xhci_driver);
|
|
|
+}
|
|
|
+module_init(xhci_mtk_init);
|
|
|
+
|
|
|
+static void __exit xhci_mtk_exit(void)
|
|
|
+{
|
|
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+ platform_driver_unregister(&mtk_xhci_driver);
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|
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+}
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|
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+module_exit(xhci_mtk_exit);
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|
|
+
|
|
|
+MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
|
|
|
+MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
|
|
|
+MODULE_LICENSE("GPL v2");
|
Chunfeng Yun