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@@ -337,19 +337,8 @@ void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
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WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL), tmp);
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}
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}
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-static int gfxhub_v1_0_early_init(void *handle)
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-{
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- return 0;
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-}
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-
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-static int gfxhub_v1_0_late_init(void *handle)
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+void gfxhub_v1_0_init(struct amdgpu_device *adev)
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{
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{
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- return 0;
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-}
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-
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-static int gfxhub_v1_0_sw_init(void *handle)
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-{
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- struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
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struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
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hub->ctx0_ptb_addr_lo32 =
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hub->ctx0_ptb_addr_lo32 =
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@@ -368,7 +357,20 @@ static int gfxhub_v1_0_sw_init(void *handle)
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
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hub->vm_l2_pro_fault_cntl =
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hub->vm_l2_pro_fault_cntl =
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
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SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
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+}
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+static int gfxhub_v1_0_early_init(void *handle)
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+{
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+ return 0;
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+}
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+
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+static int gfxhub_v1_0_late_init(void *handle)
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+{
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+ return 0;
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+}
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+
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+static int gfxhub_v1_0_sw_init(void *handle)
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+{
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return 0;
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return 0;
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}
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}
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