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@@ -44,7 +44,7 @@
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#define SOCFPGA_PLL_DIVF_SHIFT 3
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#define SOCFPGA_PLL_DIVQ_MASK 0x003F0000
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#define SOCFPGA_PLL_DIVQ_SHIFT 16
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-#define SOCFGPA_MAX_PARENTS 3
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+#define SOCFPGA_MAX_PARENTS 3
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#define SOCFPGA_L4_MP_CLK "l4_mp_clk"
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#define SOCFPGA_L4_SP_CLK "l4_sp_clk"
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@@ -258,7 +258,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
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struct clk *clk;
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struct socfpga_clk *socfpga_clk;
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const char *clk_name = node->name;
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- const char *parent_name[SOCFGPA_MAX_PARENTS];
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+ const char *parent_name[SOCFPGA_MAX_PARENTS];
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struct clk_init_data init;
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int rc;
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int i = 0;
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@@ -299,7 +299,7 @@ static void __init socfpga_gate_clk_init(struct device_node *node,
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init.name = clk_name;
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init.ops = ops;
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init.flags = 0;
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- while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
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+ while (i < SOCFPGA_MAX_PARENTS && (parent_name[i] =
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of_clk_get_parent_name(node, i)) != NULL)
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i++;
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