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@@ -214,8 +214,7 @@ static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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{
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{
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unsigned int i, res, bit, val;
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unsigned int i, res, bit, val;
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- i = 0;
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- while (i < nvec) {
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+ for (i = 0; i < nvec; i++) {
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irq_set_msi_desc_off(irq_base, i, NULL);
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irq_set_msi_desc_off(irq_base, i, NULL);
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clear_bit(pos + i, pp->msi_irq_in_use);
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clear_bit(pos + i, pp->msi_irq_in_use);
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/* Disable corresponding interrupt on MSI interrupt controller */
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/* Disable corresponding interrupt on MSI interrupt controller */
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@@ -224,7 +223,6 @@ static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val &= ~(1 << bit);
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val &= ~(1 << bit);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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- ++i;
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}
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}
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}
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}
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@@ -268,8 +266,7 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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* descs are also successfully allocated.
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* descs are also successfully allocated.
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*/
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*/
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- i = 0;
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- while (i < no_irqs) {
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+ for (i = 0; i < no_irqs; i++) {
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if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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if (irq_set_msi_desc_off(irq, i, desc) != 0) {
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clear_irq_range(pp, irq, i, pos0);
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clear_irq_range(pp, irq, i, pos0);
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goto no_valid_irq;
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goto no_valid_irq;
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@@ -281,7 +278,6 @@ static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
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val |= 1 << bit;
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val |= 1 << bit;
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
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- i++;
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}
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}
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*pos = pos0;
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*pos = pos0;
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