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@@ -771,39 +771,43 @@ gt215_ram_calc(struct nvkm_ram *base, u32 freq)
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unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
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r111100 = ram_rd32(fuc, 0x111100) & ~0x3a800000;
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- if (next->bios.ramcfg_10_02_04) {
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- switch (ram->base.type) {
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- case NVKM_RAM_TYPE_DDR3:
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- if (device->chipset != 0xa8)
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- r111100 |= 0x00000004;
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- /* no break */
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- case NVKM_RAM_TYPE_DDR2:
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- r111100 |= 0x08000000;
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- break;
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- default:
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- break;
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- }
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- } else {
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- switch (ram->base.type) {
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- case NVKM_RAM_TYPE_DDR2:
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- r111100 |= 0x1a800000;
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+ /* NVA8 seems to skip various bits related to ramcfg_10_02_04 */
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+ if (device->chipset == 0xa8) {
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+ r111100 |= 0x08000000;
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+ if (!next->bios.ramcfg_10_02_04)
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unk714 |= 0x00000010;
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- break;
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- case NVKM_RAM_TYPE_DDR3:
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- if (device->chipset == 0xa8) {
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- r111100 |= 0x08000000;
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- } else {
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- r111100 &= ~0x00000004;
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+ } else {
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+ if (next->bios.ramcfg_10_02_04) {
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+ switch (ram->base.type) {
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+ case NVKM_RAM_TYPE_DDR2:
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+ case NVKM_RAM_TYPE_DDR3:
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+ r111100 &= ~0x00000020;
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+ if (next->bios.ramcfg_10_02_10)
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+ r111100 |= 0x08000004;
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+ else
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+ r111100 |= 0x00000024;
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+ break;
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+ default:
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+ break;
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+ }
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+ } else {
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+ switch (ram->base.type) {
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+ case NVKM_RAM_TYPE_DDR2:
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+ case NVKM_RAM_TYPE_DDR3:
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+ r111100 &= ~0x00000024;
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r111100 |= 0x12800000;
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+
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+ if (next->bios.ramcfg_10_02_10)
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+ r111100 |= 0x08000000;
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+ unk714 |= 0x00000010;
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+ break;
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+ case NVKM_RAM_TYPE_GDDR3:
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+ r111100 |= 0x30000000;
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+ unk714 |= 0x00000020;
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+ break;
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+ default:
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+ break;
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}
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- unk714 |= 0x00000010;
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- break;
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- case NVKM_RAM_TYPE_GDDR3:
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- r111100 |= 0x30000000;
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- unk714 |= 0x00000020;
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- break;
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- default:
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- break;
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}
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}
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