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@@ -14,14 +14,21 @@ Required properties:
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for exynos4412/5250 controllers.
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Must be "samsung,exynos-adc-v2" for
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future controllers.
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+ Must be "samsung,exynos3250-adc" for
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+ controllers compatible with ADC of Exynos3250.
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- reg: Contains ADC register address range (base address and
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length) and the address of the phy enable register.
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- interrupts: Contains the interrupt information for the timer. The
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format is being dependent on which interrupt controller
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the Samsung device uses.
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- #io-channel-cells = <1>; As ADC has multiple outputs
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-- clocks From common clock binding: handle to adc clock.
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-- clock-names From common clock binding: Shall be "adc".
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+- clocks From common clock bindings: handles to clocks specified
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+ in "clock-names" property, in the same order.
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+- clock-names From common clock bindings: list of clock input names
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+ used by ADC block:
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+ - "adc" : ADC bus clock
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+ - "sclk" : ADC special clock (only for Exynos3250 and
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+ compatible ADC block)
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- vdd-supply VDD input supply.
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Note: child nodes can be added for auto probing from device tree.
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@@ -41,6 +48,20 @@ adc: adc@12D10000 {
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vdd-supply = <&buck5_reg>;
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};
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+Example: adding device info in dtsi file for Exynos3250 with additional sclk
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+
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+adc: adc@126C0000 {
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+ compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2;
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+ reg = <0x126C0000 0x100>, <0x10020718 0x4>;
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+ interrupts = <0 137 0>;
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+ #io-channel-cells = <1>;
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+ io-channel-ranges;
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+
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+ clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
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+ clock-names = "adc", "sclk";
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+
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+ vdd-supply = <&buck5_reg>;
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+};
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Example: Adding child nodes in dts file
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