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@@ -266,6 +266,8 @@ put_node:
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}
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#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
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+#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
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+#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
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static void imx6ul_opp_check_speed_grading(struct device *dev)
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{
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@@ -287,16 +289,30 @@ static void imx6ul_opp_check_speed_grading(struct device *dev)
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* Speed GRADING[1:0] defines the max speed of ARM:
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* 2b'00: Reserved;
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* 2b'01: 528000000Hz;
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- * 2b'10: 696000000Hz;
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- * 2b'11: Reserved;
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+ * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
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+ * 2b'11: 900000000Hz on i.MX6ULL only;
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* We need to set the max speed of ARM according to fuse map.
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*/
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val = readl_relaxed(base + OCOTP_CFG3);
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val >>= OCOTP_CFG3_SPEED_SHIFT;
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val &= 0x3;
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- if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
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- if (dev_pm_opp_disable(dev, 696000000))
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- dev_warn(dev, "failed to disable 696MHz OPP\n");
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+
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+ if (of_machine_is_compatible("fsl,imx6ul")) {
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+ if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
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+ if (dev_pm_opp_disable(dev, 696000000))
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+ dev_warn(dev, "failed to disable 696MHz OPP\n");
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+ }
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+
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+ if (of_machine_is_compatible("fsl,imx6ull")) {
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+ if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
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+ if (dev_pm_opp_disable(dev, 792000000))
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+ dev_warn(dev, "failed to disable 792MHz OPP\n");
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+
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+ if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
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+ if (dev_pm_opp_disable(dev, 900000000))
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+ dev_warn(dev, "failed to disable 900MHz OPP\n");
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+ }
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+
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iounmap(base);
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put_node:
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of_node_put(np);
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@@ -356,7 +372,8 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
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goto put_reg;
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}
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- if (of_machine_is_compatible("fsl,imx6ul"))
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+ if (of_machine_is_compatible("fsl,imx6ul") ||
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+ of_machine_is_compatible("fsl,imx6ull"))
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imx6ul_opp_check_speed_grading(cpu_dev);
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else
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imx6q_opp_check_speed_grading(cpu_dev);
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