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@@ -151,7 +151,6 @@ struct pxa3xx_nand_host {
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void *info_data;
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/* page size of attached chip */
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- unsigned int page_size;
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int use_ecc;
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int cs;
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@@ -610,12 +609,12 @@ static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
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info->buf_start += mtd->writesize;
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/* Second command setting for large pages */
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- if (host->page_size >= PAGE_CHUNK_SIZE)
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+ if (mtd->writesize >= PAGE_CHUNK_SIZE)
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info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
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case NAND_CMD_SEQIN:
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/* small page addr setting */
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- if (unlikely(host->page_size < PAGE_CHUNK_SIZE)) {
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+ if (unlikely(mtd->writesize < PAGE_CHUNK_SIZE)) {
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info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
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| (column & 0xFF);
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@@ -891,7 +890,6 @@ static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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}
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/* calculate flash information */
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- host->page_size = f->page_size;
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host->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
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/* calculate addressing information */
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@@ -930,11 +928,9 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
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if (ndcr & NDCR_PAGE_SZ) {
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/* Controller's FIFO size */
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info->fifo_size = 2048;
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- host->page_size = 2048;
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host->read_id_bytes = 4;
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} else {
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info->fifo_size = 512;
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- host->page_size = 512;
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host->read_id_bytes = 2;
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}
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@@ -1102,7 +1098,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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def = pxa3xx_flash_ids;
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KEEP_CONFIG:
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chip->ecc.mode = NAND_ECC_HW;
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- chip->ecc.size = host->page_size;
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+ chip->ecc.size = info->fifo_size;
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chip->ecc.strength = 1;
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if (info->reg_ndcr & NDCR_DWIDTH_M)
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