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@@ -2017,19 +2017,6 @@ static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
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bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
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bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
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}
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}
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-static int bcmgenet_wol_resume(struct bcmgenet_priv *priv)
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-{
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- /* From WOL-enabled suspend, switch to regular clock */
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- if (priv->wolopts)
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- clk_disable_unprepare(priv->clk_wol);
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-
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- phy_init_hw(priv->phydev);
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- /* Speed settings must be restored */
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- bcmgenet_mii_config(priv->dev);
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-
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- return 0;
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-}
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-
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/* Returns a reusable dma control register value */
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/* Returns a reusable dma control register value */
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static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
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static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
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{
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{
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@@ -2683,9 +2670,13 @@ static int bcmgenet_resume(struct device *d)
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if (ret)
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if (ret)
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goto out_clk_disable;
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goto out_clk_disable;
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- ret = bcmgenet_wol_resume(priv);
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- if (ret)
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- goto out_clk_disable;
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+ /* From WOL-enabled suspend, switch to regular clock */
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+ if (priv->wolopts)
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+ clk_disable_unprepare(priv->clk_wol);
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+
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+ phy_init_hw(priv->phydev);
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+ /* Speed settings must be restored */
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+ bcmgenet_mii_config(priv->dev);
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/* disable ethernet MAC while updating its registers */
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/* disable ethernet MAC while updating its registers */
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umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
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umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
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