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@@ -378,6 +378,13 @@ static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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+ if (bus->parent->number == rockchip->root_bus_nr)
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+ rockchip_pcie_cfg_configuration_accesses(rockchip,
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+ AXI_WRAPPER_TYPE0_CFG);
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+ else
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+ rockchip_pcie_cfg_configuration_accesses(rockchip,
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+ AXI_WRAPPER_TYPE1_CFG);
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+
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if (size == 4) {
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*val = readl(rockchip->reg_base + busdev);
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} else if (size == 2) {
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@@ -402,6 +409,13 @@ static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
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if (!IS_ALIGNED(busdev, size))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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+ if (bus->parent->number == rockchip->root_bus_nr)
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+ rockchip_pcie_cfg_configuration_accesses(rockchip,
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+ AXI_WRAPPER_TYPE0_CFG);
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+ else
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+ rockchip_pcie_cfg_configuration_accesses(rockchip,
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+ AXI_WRAPPER_TYPE1_CFG);
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+
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if (size == 4)
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writel(val, rockchip->reg_base + busdev);
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else if (size == 2)
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