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+/*
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+ * Copyright © 2006-2017 Intel Corporation
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice (including the next
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+ * paragraph) shall be included in all copies or substantial portions of the
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+ * Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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+ * IN THE SOFTWARE.
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+ *
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+ */
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+
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+#ifndef _INTEL_DISPLAY_H_
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+#define _INTEL_DISPLAY_H_
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+
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+enum pipe {
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+ INVALID_PIPE = -1,
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+
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+ PIPE_A = 0,
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+ PIPE_B,
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+ PIPE_C,
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+ _PIPE_EDP,
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+
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+ I915_MAX_PIPES = _PIPE_EDP
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+};
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+
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+#define pipe_name(p) ((p) + 'A')
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+
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+enum transcoder {
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+ TRANSCODER_A = 0,
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+ TRANSCODER_B,
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+ TRANSCODER_C,
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+ TRANSCODER_EDP,
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+ TRANSCODER_DSI_A,
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+ TRANSCODER_DSI_C,
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+
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+ I915_MAX_TRANSCODERS
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+};
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+
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+static inline const char *transcoder_name(enum transcoder transcoder)
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+{
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+ switch (transcoder) {
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+ case TRANSCODER_A:
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+ return "A";
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+ case TRANSCODER_B:
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+ return "B";
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+ case TRANSCODER_C:
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+ return "C";
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+ case TRANSCODER_EDP:
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+ return "EDP";
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+ case TRANSCODER_DSI_A:
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+ return "DSI A";
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+ case TRANSCODER_DSI_C:
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+ return "DSI C";
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+ default:
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+ return "<invalid>";
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+ }
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+}
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+
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+static inline bool transcoder_is_dsi(enum transcoder transcoder)
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+{
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+ return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
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+}
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+
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+/*
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+ * Global legacy plane identifier. Valid only for primary/sprite
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+ * planes on pre-g4x, and only for primary planes on g4x-bdw.
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+ */
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+enum i9xx_plane_id {
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+ PLANE_A,
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+ PLANE_B,
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+ PLANE_C,
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+};
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+
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+#define plane_name(p) ((p) + 'A')
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+#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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+
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+/*
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+ * Per-pipe plane identifier.
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+ * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
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+ * number of planes per CRTC. Not all platforms really have this many planes,
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+ * which means some arrays of size I915_MAX_PLANES may have unused entries
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+ * between the topmost sprite plane and the cursor plane.
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+ *
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+ * This is expected to be passed to various register macros
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+ * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
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+ */
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+enum plane_id {
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+ PLANE_PRIMARY,
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+ PLANE_SPRITE0,
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+ PLANE_SPRITE1,
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+ PLANE_SPRITE2,
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+ PLANE_CURSOR,
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+
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+ I915_MAX_PLANES,
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+};
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+
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+#define for_each_plane_id_on_crtc(__crtc, __p) \
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+ for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
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+ for_each_if((__crtc)->plane_ids_mask & BIT(__p))
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+
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+enum port {
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+ PORT_NONE = -1,
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+
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+ PORT_A = 0,
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+ PORT_B,
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+ PORT_C,
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+ PORT_D,
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+ PORT_E,
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+
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+ I915_MAX_PORTS
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+};
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+
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+#define port_name(p) ((p) + 'A')
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+
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+enum dpio_channel {
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+ DPIO_CH0,
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+ DPIO_CH1
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+};
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+
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+enum dpio_phy {
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+ DPIO_PHY0,
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+ DPIO_PHY1,
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+ DPIO_PHY2,
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+};
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+
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+#define I915_NUM_PHYS_VLV 2
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+
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+enum intel_display_power_domain {
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+ POWER_DOMAIN_PIPE_A,
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+ POWER_DOMAIN_PIPE_B,
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+ POWER_DOMAIN_PIPE_C,
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+ POWER_DOMAIN_PIPE_A_PANEL_FITTER,
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+ POWER_DOMAIN_PIPE_B_PANEL_FITTER,
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+ POWER_DOMAIN_PIPE_C_PANEL_FITTER,
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+ POWER_DOMAIN_TRANSCODER_A,
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+ POWER_DOMAIN_TRANSCODER_B,
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+ POWER_DOMAIN_TRANSCODER_C,
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+ POWER_DOMAIN_TRANSCODER_EDP,
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+ POWER_DOMAIN_TRANSCODER_DSI_A,
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+ POWER_DOMAIN_TRANSCODER_DSI_C,
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+ POWER_DOMAIN_PORT_DDI_A_LANES,
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+ POWER_DOMAIN_PORT_DDI_B_LANES,
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+ POWER_DOMAIN_PORT_DDI_C_LANES,
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+ POWER_DOMAIN_PORT_DDI_D_LANES,
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+ POWER_DOMAIN_PORT_DDI_E_LANES,
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+ POWER_DOMAIN_PORT_DDI_A_IO,
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+ POWER_DOMAIN_PORT_DDI_B_IO,
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+ POWER_DOMAIN_PORT_DDI_C_IO,
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+ POWER_DOMAIN_PORT_DDI_D_IO,
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+ POWER_DOMAIN_PORT_DDI_E_IO,
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+ POWER_DOMAIN_PORT_DSI,
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+ POWER_DOMAIN_PORT_CRT,
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+ POWER_DOMAIN_PORT_OTHER,
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+ POWER_DOMAIN_VGA,
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+ POWER_DOMAIN_AUDIO,
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+ POWER_DOMAIN_PLLS,
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+ POWER_DOMAIN_AUX_A,
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+ POWER_DOMAIN_AUX_B,
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+ POWER_DOMAIN_AUX_C,
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+ POWER_DOMAIN_AUX_D,
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+ POWER_DOMAIN_GMBUS,
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+ POWER_DOMAIN_MODESET,
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+ POWER_DOMAIN_GT_IRQ,
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+ POWER_DOMAIN_INIT,
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+
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+ POWER_DOMAIN_NUM,
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+};
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+
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+#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
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+#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
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+ ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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+#define POWER_DOMAIN_TRANSCODER(tran) \
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+ ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
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+ (tran) + POWER_DOMAIN_TRANSCODER_A)
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+
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+/* Used by dp and fdi links */
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+struct intel_link_m_n {
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+ u32 tu;
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+ u32 gmch_m;
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+ u32 gmch_n;
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+ u32 link_m;
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+ u32 link_n;
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+};
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+
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+#define for_each_pipe(__dev_priv, __p) \
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+ for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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+
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+#define for_each_pipe_masked(__dev_priv, __p, __mask) \
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+ for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
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+ for_each_if((__mask) & BIT(__p))
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+
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+#define for_each_universal_plane(__dev_priv, __pipe, __p) \
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+ for ((__p) = 0; \
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+ (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
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+ (__p)++)
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+
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+#define for_each_sprite(__dev_priv, __p, __s) \
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+ for ((__s) = 0; \
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+ (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
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+ (__s)++)
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+
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+#define for_each_port_masked(__port, __ports_mask) \
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+ for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
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+ for_each_if((__ports_mask) & BIT(__port))
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+
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+#define for_each_crtc(dev, crtc) \
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+ list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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+
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+#define for_each_intel_plane(dev, intel_plane) \
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+ list_for_each_entry(intel_plane, \
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+ &(dev)->mode_config.plane_list, \
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+ base.head)
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+
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+#define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
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+ list_for_each_entry(intel_plane, \
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+ &(dev)->mode_config.plane_list, \
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+ base.head) \
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+ for_each_if((plane_mask) & \
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+ BIT(drm_plane_index(&intel_plane->base)))
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+
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+#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
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+ list_for_each_entry(intel_plane, \
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+ &(dev)->mode_config.plane_list, \
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+ base.head) \
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+ for_each_if((intel_plane)->pipe == (intel_crtc)->pipe)
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+
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+#define for_each_intel_crtc(dev, intel_crtc) \
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+ list_for_each_entry(intel_crtc, \
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+ &(dev)->mode_config.crtc_list, \
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+ base.head)
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+
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+#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
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+ list_for_each_entry(intel_crtc, \
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+ &(dev)->mode_config.crtc_list, \
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+ base.head) \
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+ for_each_if((crtc_mask) & BIT(drm_crtc_index(&intel_crtc->base)))
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+
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+#define for_each_intel_encoder(dev, intel_encoder) \
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+ list_for_each_entry(intel_encoder, \
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+ &(dev)->mode_config.encoder_list, \
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+ base.head)
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+
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+#define for_each_intel_connector_iter(intel_connector, iter) \
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+ while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))
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+
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+#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
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+ list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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+ for_each_if((intel_encoder)->base.crtc == (__crtc))
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+
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+#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
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+ list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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+ for_each_if((intel_connector)->base.encoder == (__encoder))
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+
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+#define for_each_power_domain(domain, mask) \
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+ for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
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+ for_each_if(BIT_ULL(domain) & (mask))
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+
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+#define for_each_power_well(__dev_priv, __power_well) \
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+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
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+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
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+ (__dev_priv)->power_domains.power_well_count; \
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+ (__power_well)++)
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+
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+#define for_each_power_well_rev(__dev_priv, __power_well) \
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+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
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+ (__dev_priv)->power_domains.power_well_count - 1; \
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+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
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+ (__power_well)--)
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+
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+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
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+ for_each_power_well(__dev_priv, __power_well) \
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+ for_each_if((__power_well)->domains & (__domain_mask))
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+
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+#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
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+ for_each_power_well_rev(__dev_priv, __power_well) \
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+ for_each_if((__power_well)->domains & (__domain_mask))
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+
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+#define for_each_new_intel_plane_in_state(__state, plane, new_plane_state, __i) \
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+ for ((__i) = 0; \
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+ (__i) < (__state)->base.dev->mode_config.num_total_plane && \
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+ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
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+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
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+ (__i)++) \
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+ for_each_if(plane)
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+
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+#define for_each_new_intel_crtc_in_state(__state, crtc, new_crtc_state, __i) \
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+ for ((__i) = 0; \
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+ (__i) < (__state)->base.dev->mode_config.num_crtc && \
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+ ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
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+ (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
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+ (__i)++) \
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+ for_each_if(crtc)
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+
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+#define for_each_oldnew_intel_plane_in_state(__state, plane, old_plane_state, new_plane_state, __i) \
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+ for ((__i) = 0; \
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+ (__i) < (__state)->base.dev->mode_config.num_total_plane && \
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+ ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
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+ (old_plane_state) = to_intel_plane_state((__state)->base.planes[__i].old_state), \
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+ (new_plane_state) = to_intel_plane_state((__state)->base.planes[__i].new_state), 1); \
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+ (__i)++) \
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+ for_each_if(plane)
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+
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+void intel_link_compute_m_n(int bpp, int nlanes,
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+ int pixel_clock, int link_clock,
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+ struct intel_link_m_n *m_n,
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+ bool reduce_m_n);
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+
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+#endif
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Michal Wajdeczko