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@@ -237,15 +237,21 @@ static DEVICE_ATTR(fastsleep_workaround_applyonce, 0600,
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show_fastsleep_workaround_applyonce,
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store_fastsleep_workaround_applyonce);
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+/*
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+ * The default stop state that will be used by ppc_md.power_save
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+ * function on platforms that support stop instruction.
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+ */
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+u64 pnv_default_stop_val;
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+u64 pnv_default_stop_mask;
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/*
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* Used for ppc_md.power_save which needs a function with no parameters
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*/
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static void power9_idle(void)
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{
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- /* Requesting stop state 0 */
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- power9_idle_stop(0);
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+ power9_idle_stop(pnv_default_stop_val, pnv_default_stop_mask);
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}
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+
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/*
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* First deep stop state. Used to figure out when to save/restore
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* hypervisor context.
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@@ -253,9 +259,11 @@ static void power9_idle(void)
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u64 pnv_first_deep_stop_state = MAX_STOP_STATE;
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/*
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- * Deepest stop idle state. Used when a cpu is offlined
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+ * psscr value and mask of the deepest stop idle state.
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+ * Used when a cpu is offlined.
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*/
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-u64 pnv_deepest_stop_state;
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+u64 pnv_deepest_stop_psscr_val;
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+u64 pnv_deepest_stop_psscr_mask;
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/*
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* Power ISA 3.0 idle initialization.
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@@ -292,6 +300,44 @@ u64 pnv_deepest_stop_state;
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* Bits 60:63 - Requested Level
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* Used to specify which power-saving level must be entered on executing
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* stop instruction
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+ */
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+
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+int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags)
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+{
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+ int err = 0;
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+
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+ /*
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+ * psscr_mask == 0xf indicates an older firmware.
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+ * Set remaining fields of psscr to the default values.
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+ * See NOTE above definition of PSSCR_HV_DEFAULT_VAL
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+ */
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+ if (*psscr_mask == 0xf) {
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+ *psscr_val = *psscr_val | PSSCR_HV_DEFAULT_VAL;
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+ *psscr_mask = PSSCR_HV_DEFAULT_MASK;
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+ return err;
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+ }
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+
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+ /*
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+ * New firmware is expected to set the psscr_val bits correctly.
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+ * Validate that the following invariants are correctly maintained by
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+ * the new firmware.
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+ * - ESL bit value matches the EC bit value.
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+ * - ESL bit is set for all the deep stop states.
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+ */
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+ if (GET_PSSCR_ESL(*psscr_val) != GET_PSSCR_EC(*psscr_val)) {
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+ err = ERR_EC_ESL_MISMATCH;
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+ } else if ((flags & OPAL_PM_LOSE_FULL_CONTEXT) &&
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+ GET_PSSCR_ESL(*psscr_val) == 0) {
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+ err = ERR_DEEP_STATE_ESL_MISMATCH;
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+ }
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+
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+ return err;
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+}
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+
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+/*
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+ * pnv_arch300_idle_init: Initializes the default idle state, first
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+ * deep idle state and deepest idle state on
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+ * ISA 3.0 CPUs.
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*
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* @np: /ibm,opal/power-mgt device node
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* @flags: cpu-idle-state-flags array
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@@ -302,43 +348,109 @@ static int __init pnv_power9_idle_init(struct device_node *np, u32 *flags,
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int dt_idle_states)
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{
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u64 *psscr_val = NULL;
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+ u64 *psscr_mask = NULL;
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+ u32 *residency_ns = NULL;
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+ u64 max_residency_ns = 0;
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int rc = 0, i;
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+ bool default_stop_found = false, deepest_stop_found = false;
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- psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val),
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- GFP_KERNEL);
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- if (!psscr_val) {
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+ psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val), GFP_KERNEL);
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+ psscr_mask = kcalloc(dt_idle_states, sizeof(*psscr_mask), GFP_KERNEL);
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+ residency_ns = kcalloc(dt_idle_states, sizeof(*residency_ns),
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+ GFP_KERNEL);
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+
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+ if (!psscr_val || !psscr_mask || !residency_ns) {
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rc = -1;
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goto out;
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}
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+
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if (of_property_read_u64_array(np,
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"ibm,cpu-idle-state-psscr",
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psscr_val, dt_idle_states)) {
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- pr_warn("cpuidle-powernv: missing ibm,cpu-idle-states-psscr in DT\n");
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+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n");
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+ rc = -1;
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+ goto out;
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+ }
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+
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+ if (of_property_read_u64_array(np,
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+ "ibm,cpu-idle-state-psscr-mask",
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+ psscr_mask, dt_idle_states)) {
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+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n");
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+ rc = -1;
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+ goto out;
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+ }
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+
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+ if (of_property_read_u32_array(np,
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+ "ibm,cpu-idle-state-residency-ns",
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+ residency_ns, dt_idle_states)) {
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+ pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n");
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rc = -1;
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goto out;
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}
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/*
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- * Set pnv_first_deep_stop_state and pnv_deepest_stop_state.
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+ * Set pnv_first_deep_stop_state, pnv_deepest_stop_psscr_{val,mask},
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+ * and the pnv_default_stop_{val,mask}.
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+ *
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* pnv_first_deep_stop_state should be set to the first stop
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* level to cause hypervisor state loss.
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- * pnv_deepest_stop_state should be set to the deepest stop
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- * stop state.
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+ *
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+ * pnv_deepest_stop_{val,mask} should be set to values corresponding to
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+ * the deepest stop state.
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+ *
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+ * pnv_default_stop_{val,mask} should be set to values corresponding to
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+ * the shallowest (OPAL_PM_STOP_INST_FAST) loss-less stop state.
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*/
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pnv_first_deep_stop_state = MAX_STOP_STATE;
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for (i = 0; i < dt_idle_states; i++) {
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+ int err;
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u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK;
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if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) &&
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(pnv_first_deep_stop_state > psscr_rl))
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pnv_first_deep_stop_state = psscr_rl;
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- if (pnv_deepest_stop_state < psscr_rl)
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- pnv_deepest_stop_state = psscr_rl;
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+ err = validate_psscr_val_mask(&psscr_val[i], &psscr_mask[i],
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+ flags[i]);
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+ if (err) {
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+ report_invalid_psscr_val(psscr_val[i], err);
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+ continue;
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+ }
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+
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+ if (max_residency_ns < residency_ns[i]) {
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+ max_residency_ns = residency_ns[i];
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+ pnv_deepest_stop_psscr_val = psscr_val[i];
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+ pnv_deepest_stop_psscr_mask = psscr_mask[i];
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+ deepest_stop_found = true;
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+ }
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+
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+ if (!default_stop_found &&
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+ (flags[i] & OPAL_PM_STOP_INST_FAST)) {
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+ pnv_default_stop_val = psscr_val[i];
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+ pnv_default_stop_mask = psscr_mask[i];
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+ default_stop_found = true;
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+ }
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+ }
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+
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+ if (!default_stop_found) {
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+ pnv_default_stop_val = PSSCR_HV_DEFAULT_VAL;
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+ pnv_default_stop_mask = PSSCR_HV_DEFAULT_MASK;
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+ pr_warn("Setting default stop psscr val=0x%016llx,mask=0x%016llx\n",
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+ pnv_default_stop_val, pnv_default_stop_mask);
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+ }
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+
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+ if (!deepest_stop_found) {
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+ pnv_deepest_stop_psscr_val = PSSCR_HV_DEFAULT_VAL;
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+ pnv_deepest_stop_psscr_mask = PSSCR_HV_DEFAULT_MASK;
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+ pr_warn("Setting default stop psscr val=0x%016llx,mask=0x%016llx\n",
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+ pnv_deepest_stop_psscr_val,
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+ pnv_deepest_stop_psscr_mask);
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}
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out:
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kfree(psscr_val);
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+ kfree(psscr_mask);
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+ kfree(residency_ns);
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return rc;
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}
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Gautham R. Shenoy