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@@ -330,12 +330,14 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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u32 xcsr, count = 100;
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/*
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- * The transmitter bit clock and frame sync are to be
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- * used by both the transmitter and receiver.
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+ * Asynchronous mode: Clear SYNC for both Tx and Rx.
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+ * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
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+ * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
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*/
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- regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC, 0);
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+ regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
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+ sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
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regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
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- FSL_SAI_CR2_SYNC);
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+ sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
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/*
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* It is recommended that the transmitter is the last enabled
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@@ -625,6 +627,26 @@ static int fsl_sai_probe(struct platform_device *pdev)
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return ret;
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}
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+ /* Sync Tx with Rx as default by following old DT binding */
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+ sai->synchronous[RX] = true;
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+ sai->synchronous[TX] = false;
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+ fsl_sai_dai.symmetric_rates = 1;
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+ fsl_sai_dai.symmetric_channels = 1;
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+ fsl_sai_dai.symmetric_samplebits = 1;
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+
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+ if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
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+ /* Sync Rx with Tx */
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+ sai->synchronous[RX] = false;
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+ sai->synchronous[TX] = true;
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+ } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
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+ /* Discard all settings for asynchronous mode */
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+ sai->synchronous[RX] = false;
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+ sai->synchronous[TX] = false;
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+ fsl_sai_dai.symmetric_rates = 0;
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+ fsl_sai_dai.symmetric_channels = 0;
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+ fsl_sai_dai.symmetric_samplebits = 0;
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+ }
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+
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sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
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sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
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sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
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