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@@ -294,26 +294,41 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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}
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dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux");
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- if (IS_ERR(dpaux->rst))
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+ if (IS_ERR(dpaux->rst)) {
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+ dev_err(&pdev->dev, "failed to get reset control: %ld\n",
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+ PTR_ERR(dpaux->rst));
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return PTR_ERR(dpaux->rst);
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+ }
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dpaux->clk = devm_clk_get(&pdev->dev, NULL);
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- if (IS_ERR(dpaux->clk))
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+ if (IS_ERR(dpaux->clk)) {
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+ dev_err(&pdev->dev, "failed to get module clock: %ld\n",
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+ PTR_ERR(dpaux->clk));
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return PTR_ERR(dpaux->clk);
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+ }
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err = clk_prepare_enable(dpaux->clk);
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- if (err < 0)
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+ if (err < 0) {
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+ dev_err(&pdev->dev, "failed to enable module clock: %d\n",
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+ err);
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return err;
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+ }
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reset_control_deassert(dpaux->rst);
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dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent");
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- if (IS_ERR(dpaux->clk_parent))
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+ if (IS_ERR(dpaux->clk_parent)) {
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+ dev_err(&pdev->dev, "failed to get parent clock: %ld\n",
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+ PTR_ERR(dpaux->clk_parent));
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return PTR_ERR(dpaux->clk_parent);
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+ }
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err = clk_prepare_enable(dpaux->clk_parent);
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- if (err < 0)
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+ if (err < 0) {
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+ dev_err(&pdev->dev, "failed to enable parent clock: %d\n",
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+ err);
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return err;
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+ }
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err = clk_set_rate(dpaux->clk_parent, 270000000);
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if (err < 0) {
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@@ -323,8 +338,11 @@ static int tegra_dpaux_probe(struct platform_device *pdev)
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}
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dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd");
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- if (IS_ERR(dpaux->vdd))
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+ if (IS_ERR(dpaux->vdd)) {
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+ dev_err(&pdev->dev, "failed to get VDD supply: %ld\n",
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+ PTR_ERR(dpaux->vdd));
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return PTR_ERR(dpaux->vdd);
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+ }
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err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0,
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dev_name(dpaux->dev), dpaux);
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