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@@ -22,7 +22,8 @@ ENTRY(v5t_early_abort)
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
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ldreq r3, [r4] @ read aborted ARM instruction
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ldreq r3, [r4] @ read aborted ARM instruction
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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bic r1, r1, #1 << 11 @ clear bits 11 of FSR
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- do_ldrd_abort tmp=ip, insn=r3
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+ teq_ldrd tmp=ip, insn=r3 @ insn was LDRD?
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+ beq do_DataAbort @ yes
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tst r3, #1 << 20 @ check write
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tst r3, #1 << 20 @ check write
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orreq r1, r1, #1 << 11
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orreq r1, r1, #1 << 11
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b do_DataAbort
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b do_DataAbort
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