|
@@ -30,8 +30,7 @@ Second type has a dedicated interrupt per gpio bank.
|
|
|
|
|
|
Pin controller node:
|
|
|
Required properties:
|
|
|
-- compatible : should be "st,<SOC>-<pio-block>-pinctrl"
|
|
|
- like st,stih415-sbc-pinctrl, st,stih415-front-pinctrl and so on.
|
|
|
+- compatible : should be "st,stih407-<pio-block>-pinctrl"
|
|
|
- st,syscfg : Should be a phandle of the syscfg node.
|
|
|
- st,retime-pin-mask : Should be mask to specify which pins can be retimed.
|
|
|
If the property is not present, it is assumed that all the pins in the
|
|
@@ -80,23 +79,23 @@ include/dt-bindings/interrupt-controller/irq.h
|
|
|
|
|
|
Example:
|
|
|
pin-controller-sbc {
|
|
|
- #address-cells = <1>;
|
|
|
- #size-cells = <1>;
|
|
|
- compatible = "st,stih415-sbc-pinctrl";
|
|
|
- st,syscfg = <&syscfg_sbc>;
|
|
|
- reg = <0xfe61f080 0x4>;
|
|
|
- reg-names = "irqmux";
|
|
|
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- interrupt-names = "irqmux";
|
|
|
- ranges = <0 0xfe610000 0x5000>;
|
|
|
-
|
|
|
- PIO0: gpio@fe610000 {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <1>;
|
|
|
+ compatible = "st,stih407-sbc-pinctrl";
|
|
|
+ st,syscfg = <&syscfg_sbc>;
|
|
|
+ reg = <0x0961f080 0x4>;
|
|
|
+ reg-names = "irqmux";
|
|
|
+ interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
|
|
|
+ interrupt-names = "irqmux";
|
|
|
+ ranges = <0 0x09610000 0x6000>;
|
|
|
+
|
|
|
+ pio0: gpio@09610000 {
|
|
|
gpio-controller;
|
|
|
- #gpio-cells = <2>;
|
|
|
+ #gpio-cells = <2>;
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <2>;
|
|
|
- reg = <0 0x100>;
|
|
|
- st,bank-name = "PIO0";
|
|
|
+ reg = <0x0 0x100>;
|
|
|
+ st,bank-name = "PIO0";
|
|
|
};
|
|
|
...
|
|
|
pin-functions nodes follow...
|
|
@@ -166,7 +165,7 @@ pin-controller {
|
|
|
|
|
|
sdhci0:sdhci@fe810000{
|
|
|
...
|
|
|
- interrupt-parent = <&PIO3>;
|
|
|
+ interrupt-parent = <&pio3>;
|
|
|
#interrupt-cells = <2>;
|
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
|
|
|
interrupt-names = "card-detect";
|