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@@ -241,6 +241,35 @@ static inline void out_be64(volatile u64 __iomem *addr, u64 val)
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#endif
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#endif
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#endif /* __powerpc64__ */
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#endif /* __powerpc64__ */
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+
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+/*
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+ * Simple Cache inhibited accessors
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+ * Unlike the DEF_MMIO_* macros, these don't include any h/w memory
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+ * barriers, callers need to manage memory barriers on their own.
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+ * These can only be used in hypervisor real mode.
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+ */
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+
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+static inline u32 _lwzcix(unsigned long addr)
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+{
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+ u32 ret;
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+
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+ __asm__ __volatile__("lwzcix %0,0, %1"
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+ : "=r" (ret) : "r" (addr) : "memory");
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+ return ret;
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+}
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+
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+static inline void _stbcix(u64 addr, u8 val)
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+{
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+ __asm__ __volatile__("stbcix %0,0,%1"
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+ : : "r" (val), "r" (addr) : "memory");
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+}
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+
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+static inline void _stwcix(u64 addr, u32 val)
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+{
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+ __asm__ __volatile__("stwcix %0,0,%1"
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+ : : "r" (val), "r" (addr) : "memory");
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+}
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+
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/*
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/*
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* Low level IO stream instructions are defined out of line for now
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* Low level IO stream instructions are defined out of line for now
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*/
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*/
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