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@@ -98,7 +98,9 @@ read_pll(struct drm_device *dev, int clk, u32 pll)
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sclk = read_clk(dev, 0x10 + clk, false);
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}
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- return sclk * N / (M * P);
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+ if (M * P)
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+ return sclk * N / (M * P);
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+ return 0;
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}
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struct creg {
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@@ -182,23 +184,26 @@ prog_pll(struct drm_device *dev, int clk, u32 pll, struct creg *reg)
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const u32 src1 = 0x004160 + (clk * 4);
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const u32 ctrl = pll + 0;
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const u32 coef = pll + 4;
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- u32 cntl;
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if (!reg->clk && !reg->pll) {
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NV_DEBUG(dev, "no clock for %02x\n", clk);
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return;
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}
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- cntl = nv_rd32(dev, ctrl) & 0xfffffff2;
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if (reg->pll) {
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nv_mask(dev, src0, 0x00000101, 0x00000101);
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nv_wr32(dev, coef, reg->pll);
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- nv_wr32(dev, ctrl, cntl | 0x00000015);
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+ nv_mask(dev, ctrl, 0x00000015, 0x00000015);
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+ nv_mask(dev, ctrl, 0x00000010, 0x00000000);
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+ nv_wait(dev, ctrl, 0x00020000, 0x00020000);
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+ nv_mask(dev, ctrl, 0x00000010, 0x00000010);
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+ nv_mask(dev, ctrl, 0x00000008, 0x00000000);
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nv_mask(dev, src1, 0x00000100, 0x00000000);
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nv_mask(dev, src1, 0x00000001, 0x00000000);
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} else {
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nv_mask(dev, src1, 0x003f3141, 0x00000101 | reg->clk);
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- nv_wr32(dev, ctrl, cntl | 0x0000001d);
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+ nv_mask(dev, ctrl, 0x00000018, 0x00000018);
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+ udelay(20);
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nv_mask(dev, ctrl, 0x00000001, 0x00000000);
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nv_mask(dev, src0, 0x00000100, 0x00000000);
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nv_mask(dev, src0, 0x00000001, 0x00000000);
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