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@@ -48,6 +48,13 @@ MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
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MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
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MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
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+MODULE_FIRMWARE("amdgpu/raven_ce.bin");
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+MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
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+MODULE_FIRMWARE("amdgpu/raven_me.bin");
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+MODULE_FIRMWARE("amdgpu/raven_mec.bin");
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+MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
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+MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
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+
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static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
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{
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{SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
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