|
@@ -192,6 +192,9 @@
|
|
#define MT_BCN_OFFSET_BASE 0x041c
|
|
#define MT_BCN_OFFSET_BASE 0x041c
|
|
#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))
|
|
#define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))
|
|
|
|
|
|
|
|
+#define MT_RXQ_STA 0x0430
|
|
|
|
+#define MT_TXQ_STA 0x0434
|
|
|
|
+
|
|
#define MT_RF_CSR_CFG 0x0500
|
|
#define MT_RF_CSR_CFG 0x0500
|
|
#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
|
|
#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
|
|
#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
|
|
#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
|