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@@ -394,7 +394,7 @@ struct octeon_hcd {
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result = -1; \
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break; \
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} else \
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- cvmx_wait(100); \
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+ __delay(100); \
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} \
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} while (0); \
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result; })
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@@ -774,7 +774,7 @@ retry:
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usbn_clk_ctl.s.hclk_rst = 1;
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cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb->index), usbn_clk_ctl.u64);
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/* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
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- cvmx_wait(64);
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+ __delay(64);
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/*
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* 3. Program the power-on reset field in the USBN clock-control
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* register:
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@@ -795,7 +795,7 @@ retry:
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cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb->index),
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usbn_usbp_ctl_status.u64);
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/* 6. Wait 10 cycles */
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- cvmx_wait(10);
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+ __delay(10);
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/*
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* 7. Clear ATE_RESET field in the USBN clock-control register:
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* USBN_USBP_CTL_STATUS[ATE_RESET] = 0
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