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@@ -53,15 +53,23 @@
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#define EM28XX_VERSION "0.2.0"
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+static unsigned int isoc_debug;
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+module_param(isoc_debug, int, 0644);
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+MODULE_PARM_DESC(isoc_debug, "enable debug messages [isoc transfers]");
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+
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+static unsigned int disable_vbi;
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+module_param(disable_vbi, int, 0644);
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+MODULE_PARM_DESC(disable_vbi, "disable vbi support");
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+
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+static int alt;
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+module_param(alt, int, 0644);
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+MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
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+
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#define em28xx_videodbg(fmt, arg...) do {\
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if (video_debug) \
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printk(KERN_INFO "%s %s :"fmt, \
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dev->name, __func__ , ##arg); } while (0)
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-static unsigned int isoc_debug;
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-module_param(isoc_debug, int, 0644);
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-MODULE_PARM_DESC(isoc_debug, "enable debug messages [isoc transfers]");
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-
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#define em28xx_isocdbg(fmt, arg...) \
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do {\
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if (isoc_debug) { \
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@@ -135,6 +143,257 @@ static struct em28xx_fmt format[] = {
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},
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};
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+int em28xx_vbi_supported(struct em28xx *dev)
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+{
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+ /* Modprobe option to manually disable */
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+ if (disable_vbi == 1)
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+ return 0;
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+
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+ if (dev->board.is_webcam)
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+ return 0;
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+
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+ /* FIXME: check subdevices for VBI support */
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+
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+ if (dev->chip_id == CHIP_ID_EM2860 ||
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+ dev->chip_id == CHIP_ID_EM2883)
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+ return 1;
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+
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+ /* Version of em28xx that does not support VBI */
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+ return 0;
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+}
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+
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+/*
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+ * em28xx_wake_i2c()
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+ * configure i2c attached devices
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+ */
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+void em28xx_wake_i2c(struct em28xx *dev)
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+{
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+ v4l2_device_call_all(&dev->v4l2_dev, 0, core, reset, 0);
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+ v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_routing,
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+ INPUT(dev->ctl_input)->vmux, 0, 0);
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+ v4l2_device_call_all(&dev->v4l2_dev, 0, video, s_stream, 0);
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+}
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+
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+int em28xx_colorlevels_set_default(struct em28xx *dev)
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+{
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+ em28xx_write_reg(dev, EM28XX_R20_YGAIN, CONTRAST_DEFAULT);
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+ em28xx_write_reg(dev, EM28XX_R21_YOFFSET, BRIGHTNESS_DEFAULT);
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+ em28xx_write_reg(dev, EM28XX_R22_UVGAIN, SATURATION_DEFAULT);
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+ em28xx_write_reg(dev, EM28XX_R23_UOFFSET, BLUE_BALANCE_DEFAULT);
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+ em28xx_write_reg(dev, EM28XX_R24_VOFFSET, RED_BALANCE_DEFAULT);
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+ em28xx_write_reg(dev, EM28XX_R25_SHARPNESS, SHARPNESS_DEFAULT);
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+
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+ em28xx_write_reg(dev, EM28XX_R14_GAMMA, 0x20);
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+ em28xx_write_reg(dev, EM28XX_R15_RGAIN, 0x20);
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+ em28xx_write_reg(dev, EM28XX_R16_GGAIN, 0x20);
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+ em28xx_write_reg(dev, EM28XX_R17_BGAIN, 0x20);
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+ em28xx_write_reg(dev, EM28XX_R18_ROFFSET, 0x00);
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+ em28xx_write_reg(dev, EM28XX_R19_GOFFSET, 0x00);
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+ return em28xx_write_reg(dev, EM28XX_R1A_BOFFSET, 0x00);
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+}
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+
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+int em28xx_set_outfmt(struct em28xx *dev)
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+{
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+ int ret;
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+ u8 fmt, vinctrl;
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+
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+ fmt = dev->format->reg;
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+ if (!dev->is_em25xx)
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+ fmt |= 0x20;
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+ /*
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+ * NOTE: it's not clear if this is really needed !
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+ * The datasheets say bit 5 is a reserved bit and devices seem to work
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+ * fine without it. But the Windows driver sets it for em2710/50+em28xx
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+ * devices and we've always been setting it, too.
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+ *
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+ * em2765 (em25xx, em276x/7x/8x) devices do NOT work with this bit set,
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+ * it's likely used for an additional (compressed ?) format there.
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+ */
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+ ret = em28xx_write_reg(dev, EM28XX_R27_OUTFMT, fmt);
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+ if (ret < 0)
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+ return ret;
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+
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+ ret = em28xx_write_reg(dev, EM28XX_R10_VINMODE, dev->vinmode);
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+ if (ret < 0)
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+ return ret;
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+
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+ vinctrl = dev->vinctl;
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+ if (em28xx_vbi_supported(dev) == 1) {
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+ vinctrl |= EM28XX_VINCTRL_VBI_RAW;
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+ em28xx_write_reg(dev, EM28XX_R34_VBI_START_H, 0x00);
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+ em28xx_write_reg(dev, EM28XX_R36_VBI_WIDTH, dev->vbi_width/4);
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+ em28xx_write_reg(dev, EM28XX_R37_VBI_HEIGHT, dev->vbi_height);
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+ if (dev->norm & V4L2_STD_525_60) {
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+ /* NTSC */
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+ em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x09);
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+ } else if (dev->norm & V4L2_STD_625_50) {
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+ /* PAL */
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+ em28xx_write_reg(dev, EM28XX_R35_VBI_START_V, 0x07);
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+ }
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+ }
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+
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+ return em28xx_write_reg(dev, EM28XX_R11_VINCTRL, vinctrl);
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+}
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+
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+static int em28xx_accumulator_set(struct em28xx *dev, u8 xmin, u8 xmax,
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+ u8 ymin, u8 ymax)
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+{
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+ em28xx_videodbg("em28xx Scale: (%d,%d)-(%d,%d)\n",
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+ xmin, ymin, xmax, ymax);
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+
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+ em28xx_write_regs(dev, EM28XX_R28_XMIN, &xmin, 1);
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+ em28xx_write_regs(dev, EM28XX_R29_XMAX, &xmax, 1);
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+ em28xx_write_regs(dev, EM28XX_R2A_YMIN, &ymin, 1);
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+ return em28xx_write_regs(dev, EM28XX_R2B_YMAX, &ymax, 1);
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+}
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+
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+static void em28xx_capture_area_set(struct em28xx *dev, u8 hstart, u8 vstart,
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+ u16 width, u16 height)
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+{
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+ u8 cwidth = width >> 2;
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+ u8 cheight = height >> 2;
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+ u8 overflow = (height >> 9 & 0x02) | (width >> 10 & 0x01);
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+ /* NOTE: size limit: 2047x1023 = 2MPix */
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+
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+ em28xx_videodbg("capture area set to (%d,%d): %dx%d\n",
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+ hstart, vstart,
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+ ((overflow & 2) << 9 | cwidth << 2),
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+ ((overflow & 1) << 10 | cheight << 2));
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+
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+ em28xx_write_regs(dev, EM28XX_R1C_HSTART, &hstart, 1);
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+ em28xx_write_regs(dev, EM28XX_R1D_VSTART, &vstart, 1);
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+ em28xx_write_regs(dev, EM28XX_R1E_CWIDTH, &cwidth, 1);
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+ em28xx_write_regs(dev, EM28XX_R1F_CHEIGHT, &cheight, 1);
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+ em28xx_write_regs(dev, EM28XX_R1B_OFLOW, &overflow, 1);
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+
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+ /* FIXME: function/meaning of these registers ? */
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+ /* FIXME: align width+height to multiples of 4 ?! */
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+ if (dev->is_em25xx) {
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+ em28xx_write_reg(dev, 0x34, width >> 4);
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+ em28xx_write_reg(dev, 0x35, height >> 4);
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+ }
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+}
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+
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+static int em28xx_scaler_set(struct em28xx *dev, u16 h, u16 v)
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+{
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+ u8 mode;
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+ /* the em2800 scaler only supports scaling down to 50% */
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+
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+ if (dev->board.is_em2800) {
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+ mode = (v ? 0x20 : 0x00) | (h ? 0x10 : 0x00);
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+ } else {
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+ u8 buf[2];
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+
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+ buf[0] = h;
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+ buf[1] = h >> 8;
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+ em28xx_write_regs(dev, EM28XX_R30_HSCALELOW, (char *)buf, 2);
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+
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+ buf[0] = v;
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+ buf[1] = v >> 8;
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+ em28xx_write_regs(dev, EM28XX_R32_VSCALELOW, (char *)buf, 2);
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+ /* it seems that both H and V scalers must be active
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+ to work correctly */
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+ mode = (h || v) ? 0x30 : 0x00;
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+ }
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+ return em28xx_write_reg_bits(dev, EM28XX_R26_COMPR, mode, 0x30);
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+}
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+
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+/* FIXME: this only function read values from dev */
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+int em28xx_resolution_set(struct em28xx *dev)
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+{
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+ int width, height;
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+ width = norm_maxw(dev);
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+ height = norm_maxh(dev);
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+
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+ /* Properly setup VBI */
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+ dev->vbi_width = 720;
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+ if (dev->norm & V4L2_STD_525_60)
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+ dev->vbi_height = 12;
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+ else
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+ dev->vbi_height = 18;
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+
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+ em28xx_set_outfmt(dev);
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+
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+ em28xx_accumulator_set(dev, 1, (width - 4) >> 2, 1, (height - 4) >> 2);
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+
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+ /* If we don't set the start position to 2 in VBI mode, we end up
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+ with line 20/21 being YUYV encoded instead of being in 8-bit
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+ greyscale. The core of the issue is that line 21 (and line 23 for
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+ PAL WSS) are inside of active video region, and as a result they
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+ get the pixelformatting associated with that area. So by cropping
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+ it out, we end up with the same format as the rest of the VBI
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+ region */
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+ if (em28xx_vbi_supported(dev) == 1)
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+ em28xx_capture_area_set(dev, 0, 2, width, height);
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+ else
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+ em28xx_capture_area_set(dev, 0, 0, width, height);
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+
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+ return em28xx_scaler_set(dev, dev->hscale, dev->vscale);
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+}
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+
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+/* Set USB alternate setting for analog video */
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+int em28xx_set_alternate(struct em28xx *dev)
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+{
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+ int errCode;
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+ int i;
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+ unsigned int min_pkt_size = dev->width * 2 + 4;
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+
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+ /* NOTE: for isoc transfers, only alt settings > 0 are allowed
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+ bulk transfers seem to work only with alt=0 ! */
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+ dev->alt = 0;
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+ if ((alt > 0) && (alt < dev->num_alt)) {
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+ em28xx_videodbg("alternate forced to %d\n", dev->alt);
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+ dev->alt = alt;
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+ goto set_alt;
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+ }
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+ if (dev->analog_xfer_bulk)
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+ goto set_alt;
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+
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+ /* When image size is bigger than a certain value,
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+ the frame size should be increased, otherwise, only
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+ green screen will be received.
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+ */
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+ if (dev->width * 2 * dev->height > 720 * 240 * 2)
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+ min_pkt_size *= 2;
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+
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+ for (i = 0; i < dev->num_alt; i++) {
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+ /* stop when the selected alt setting offers enough bandwidth */
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+ if (dev->alt_max_pkt_size_isoc[i] >= min_pkt_size) {
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+ dev->alt = i;
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+ break;
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+ /* otherwise make sure that we end up with the maximum bandwidth
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+ because the min_pkt_size equation might be wrong...
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+ */
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+ } else if (dev->alt_max_pkt_size_isoc[i] >
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+ dev->alt_max_pkt_size_isoc[dev->alt])
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+ dev->alt = i;
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+ }
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+
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+set_alt:
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+ /* NOTE: for bulk transfers, we need to call usb_set_interface()
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+ * even if the previous settings were the same. Otherwise streaming
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+ * fails with all urbs having status = -EOVERFLOW ! */
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+ if (dev->analog_xfer_bulk) {
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+ dev->max_pkt_size = 512; /* USB 2.0 spec */
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+ dev->packet_multiplier = EM28XX_BULK_PACKET_MULTIPLIER;
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+ } else { /* isoc */
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+ em28xx_videodbg("minimum isoc packet size: %u (alt=%d)\n",
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+ min_pkt_size, dev->alt);
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+ dev->max_pkt_size =
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+ dev->alt_max_pkt_size_isoc[dev->alt];
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+ dev->packet_multiplier = EM28XX_NUM_ISOC_PACKETS;
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+ }
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+ em28xx_videodbg("setting alternate %d with wMaxPacketSize=%u\n",
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+ dev->alt, dev->max_pkt_size);
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+ errCode = usb_set_interface(dev->udev, 0, dev->alt);
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+ if (errCode < 0) {
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+ em28xx_errdev("cannot change alternate number to %d (error=%i)\n",
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+ dev->alt, errCode);
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+ return errCode;
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+ }
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+ return 0;
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+}
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+
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/* ------------------------------------------------------------------
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DMA and thread functions
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------------------------------------------------------------------*/
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@@ -1817,6 +2076,113 @@ static struct video_device *em28xx_vdev_init(struct em28xx *dev,
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return vfd;
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}
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+static void em28xx_setup_xc3028(struct em28xx *dev, struct xc2028_ctrl *ctl)
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+{
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+ memset(ctl, 0, sizeof(*ctl));
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+
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+ ctl->fname = XC2028_DEFAULT_FIRMWARE;
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+ ctl->max_len = 64;
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+ ctl->mts = em28xx_boards[dev->model].mts_firmware;
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+
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+ switch (dev->model) {
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+ case EM2880_BOARD_EMPIRE_DUAL_TV:
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+ case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
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+ case EM2882_BOARD_TERRATEC_HYBRID_XS:
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+ ctl->demod = XC3028_FE_ZARLINK456;
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+ break;
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+ case EM2880_BOARD_TERRATEC_HYBRID_XS:
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+ case EM2880_BOARD_TERRATEC_HYBRID_XS_FR:
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+ case EM2881_BOARD_PINNACLE_HYBRID_PRO:
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+ ctl->demod = XC3028_FE_ZARLINK456;
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+ break;
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+ case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
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+ case EM2882_BOARD_PINNACLE_HYBRID_PRO_330E:
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+ ctl->demod = XC3028_FE_DEFAULT;
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+ break;
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+ case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
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+ ctl->demod = XC3028_FE_DEFAULT;
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+ ctl->fname = XC3028L_DEFAULT_FIRMWARE;
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+ break;
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+ case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850:
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+ case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
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+ case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
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+ /* FIXME: Better to specify the needed IF */
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+ ctl->demod = XC3028_FE_DEFAULT;
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+ break;
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+ case EM2883_BOARD_KWORLD_HYBRID_330U:
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+ case EM2882_BOARD_DIKOM_DK300:
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+ case EM2882_BOARD_KWORLD_VS_DVBT:
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+ ctl->demod = XC3028_FE_CHINA;
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+ ctl->fname = XC2028_DEFAULT_FIRMWARE;
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+ break;
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+ case EM2882_BOARD_EVGA_INDTUBE:
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+ ctl->demod = XC3028_FE_CHINA;
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+ ctl->fname = XC3028L_DEFAULT_FIRMWARE;
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+ break;
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+ default:
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+ ctl->demod = XC3028_FE_OREN538;
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+ }
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+}
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+
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+void em28xx_tuner_setup(struct em28xx *dev)
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+{
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+ struct tuner_setup tun_setup;
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+ struct v4l2_frequency f;
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+
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+ if (dev->tuner_type == TUNER_ABSENT)
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+ return;
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+
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+ memset(&tun_setup, 0, sizeof(tun_setup));
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+
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+ tun_setup.mode_mask = T_ANALOG_TV | T_RADIO;
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+ tun_setup.tuner_callback = em28xx_tuner_callback;
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+
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+ if (dev->board.radio.type) {
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+ tun_setup.type = dev->board.radio.type;
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+ tun_setup.addr = dev->board.radio_addr;
|
|
|
+
|
|
|
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_type_addr, &tun_setup);
|
|
|
+ }
|
|
|
+
|
|
|
+ if ((dev->tuner_type != TUNER_ABSENT) && (dev->tuner_type)) {
|
|
|
+ tun_setup.type = dev->tuner_type;
|
|
|
+ tun_setup.addr = dev->tuner_addr;
|
|
|
+
|
|
|
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_type_addr, &tun_setup);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (dev->tda9887_conf) {
|
|
|
+ struct v4l2_priv_tun_config tda9887_cfg;
|
|
|
+
|
|
|
+ tda9887_cfg.tuner = TUNER_TDA9887;
|
|
|
+ tda9887_cfg.priv = &dev->tda9887_conf;
|
|
|
+
|
|
|
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_config, &tda9887_cfg);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (dev->tuner_type == TUNER_XC2028) {
|
|
|
+ struct v4l2_priv_tun_config xc2028_cfg;
|
|
|
+ struct xc2028_ctrl ctl;
|
|
|
+
|
|
|
+ memset(&xc2028_cfg, 0, sizeof(xc2028_cfg));
|
|
|
+ memset(&ctl, 0, sizeof(ctl));
|
|
|
+
|
|
|
+ em28xx_setup_xc3028(dev, &ctl);
|
|
|
+
|
|
|
+ xc2028_cfg.tuner = TUNER_XC2028;
|
|
|
+ xc2028_cfg.priv = &ctl;
|
|
|
+
|
|
|
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_config, &xc2028_cfg);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* configure tuner */
|
|
|
+ f.tuner = 0;
|
|
|
+ f.type = V4L2_TUNER_ANALOG_TV;
|
|
|
+ f.frequency = 9076; /* just a magic number */
|
|
|
+ dev->ctl_freq = f.frequency;
|
|
|
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
|
|
|
+}
|
|
|
+
|
|
|
int em28xx_register_analog_devices(struct em28xx *dev)
|
|
|
{
|
|
|
u8 val;
|
Mauro Carvalho Chehab