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@@ -48,7 +48,7 @@ static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)
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/* CCK Settings */
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phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);
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phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
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- ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
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+ rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
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phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
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}
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@@ -82,7 +82,7 @@ static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm)
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phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
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/* Tx Settings */
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phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0);
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- ODM_UpdateRxIdleAnt_88E(dm_odm, MAIN_ANT);
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+ rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
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/* antenna mapping table */
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if (!dm_odm->bIsMPChip) { /* testchip */
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@@ -184,35 +184,42 @@ void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm)
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dm_fast_training_init(dm_odm);
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}
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-void ODM_UpdateRxIdleAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant)
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+void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant)
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{
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struct fast_ant_train *dm_fat_tbl = &dm_odm->DM_FatTable;
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struct adapter *adapter = dm_odm->Adapter;
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- u32 DefaultAnt, OptionalAnt;
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-
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- if (dm_fat_tbl->RxIdleAnt != Ant) {
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- ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Need to Update Rx Idle Ant\n"));
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- if (Ant == MAIN_ANT) {
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- DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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- OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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+ u32 default_ant, optional_ant;
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+
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+ if (dm_fat_tbl->RxIdleAnt != ant) {
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+ if (ant == MAIN_ANT) {
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+ default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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+ MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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+ optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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+ AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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} else {
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- DefaultAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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- OptionalAnt = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ? MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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+ default_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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+ AUX_ANT_CG_TRX : AUX_ANT_CGCS_RX;
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+ optional_ant = (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) ?
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+ MAIN_ANT_CG_TRX : MAIN_ANT_CGCS_RX;
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}
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if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
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- phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
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- phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
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- phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N, BIT14|BIT13|BIT12, DefaultAnt); /* Default TX */
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- phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N, BIT6|BIT7, DefaultAnt); /* Resp Tx */
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+ phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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+ BIT5|BIT4|BIT3, default_ant);
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+ phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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+ BIT8|BIT7|BIT6, optional_ant);
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+ phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
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+ BIT14|BIT13|BIT12, default_ant);
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+ phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
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+ BIT6|BIT7, default_ant);
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} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
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- phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT5|BIT4|BIT3, DefaultAnt); /* Default RX */
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- phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT8|BIT7|BIT6, OptionalAnt); /* Optional RX */
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+ phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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+ BIT5|BIT4|BIT3, default_ant);
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+ phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
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+ BIT8|BIT7|BIT6, optional_ant);
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}
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}
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- dm_fat_tbl->RxIdleAnt = Ant;
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- ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT"));
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- pr_info("RxIdleAnt=%s\n", (Ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
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+ dm_fat_tbl->RxIdleAnt = ant;
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}
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static void odm_UpdateTxAnt_88E(struct odm_dm_struct *dm_odm, u8 Ant, u32 MacId)
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@@ -324,7 +331,7 @@ static void odm_HWAntDiv(struct odm_dm_struct *dm_odm)
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}
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/* 2 Set RX Idle Antenna */
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- ODM_UpdateRxIdleAnt_88E(dm_odm, RxIdleAnt);
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+ rtl88eu_dm_update_rx_idle_ant(dm_odm, RxIdleAnt);
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pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;
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pDM_DigTable->RSSI_max = MaxRSSI;
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