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@@ -1248,6 +1248,35 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring,
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return wa_ctx_end(wa_ctx, *offset = index, 1);
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}
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+static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring,
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+ struct i915_wa_ctx_bb *wa_ctx,
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+ uint32_t *const batch,
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+ uint32_t *offset)
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+{
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+ uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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+
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+ /* FIXME: Replace me with WA */
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+ wa_ctx_emit(batch, index, MI_NOOP);
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+
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+ /* Pad to end of cacheline */
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+ while (index % CACHELINE_DWORDS)
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+ wa_ctx_emit(batch, index, MI_NOOP);
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+
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+ return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
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+}
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+
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+static int gen9_init_perctx_bb(struct intel_engine_cs *ring,
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+ struct i915_wa_ctx_bb *wa_ctx,
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+ uint32_t *const batch,
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+ uint32_t *offset)
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+{
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+ uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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+
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+ wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
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+
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+ return wa_ctx_end(wa_ctx, *offset = index, 1);
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+}
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+
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static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size)
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{
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int ret;
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@@ -1289,10 +1318,11 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring)
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WARN_ON(ring->id != RCS);
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/* update this when WA for higher Gen are added */
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- if (WARN(INTEL_INFO(ring->dev)->gen > 8,
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- "WA batch buffer is not initialized for Gen%d\n",
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- INTEL_INFO(ring->dev)->gen))
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+ if (INTEL_INFO(ring->dev)->gen > 9) {
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+ DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
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+ INTEL_INFO(ring->dev)->gen);
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return 0;
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+ }
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/* some WA perform writes to scratch page, ensure it is valid */
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if (ring->scratch.obj == NULL) {
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@@ -1324,6 +1354,20 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring)
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&offset);
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if (ret)
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goto out;
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+ } else if (INTEL_INFO(ring->dev)->gen == 9) {
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+ ret = gen9_init_indirectctx_bb(ring,
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+ &wa_ctx->indirect_ctx,
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+ batch,
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+ &offset);
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+ if (ret)
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+ goto out;
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+
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+ ret = gen9_init_perctx_bb(ring,
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+ &wa_ctx->per_ctx,
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+ batch,
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+ &offset);
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+ if (ret)
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+ goto out;
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}
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out:
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