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@@ -66,6 +66,7 @@ struct qcom_iommu_ctx {
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void __iomem *base;
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bool secure_init;
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u8 asid; /* asid and ctx bank # are 1:1 */
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+ struct iommu_domain *domain;
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};
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struct qcom_iommu_domain {
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@@ -194,12 +195,15 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
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fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
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iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
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- dev_err_ratelimited(ctx->dev,
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- "Unhandled context fault: fsr=0x%x, "
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- "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
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- fsr, iova, fsynr, ctx->asid);
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+ if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
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+ dev_err_ratelimited(ctx->dev,
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+ "Unhandled context fault: fsr=0x%x, "
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+ "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
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+ fsr, iova, fsynr, ctx->asid);
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+ }
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iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
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+ iommu_writel(ctx, ARM_SMMU_CB_RESUME, RESUME_TERMINATE);
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return IRQ_HANDLED;
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}
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@@ -274,12 +278,14 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
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/* SCTLR */
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reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
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- SCTLR_M | SCTLR_S1_ASIDPNE;
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+ SCTLR_M | SCTLR_S1_ASIDPNE | SCTLR_CFCFG;
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if (IS_ENABLED(CONFIG_BIG_ENDIAN))
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reg |= SCTLR_E;
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iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
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+
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+ ctx->domain = domain;
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}
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mutex_unlock(&qcom_domain->init_mutex);
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@@ -395,6 +401,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de
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/* Disable the context bank: */
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iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
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+
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+ ctx->domain = NULL;
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}
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pm_runtime_put_sync(qcom_iommu->dev);
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