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+* Allwinner sun8i GMAC ethernet controller
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+
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+This device is a platform glue layer for stmmac.
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+Please see stmmac.txt for the other unchanged properties.
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+
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+Required properties:
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+- compatible: should be one of the following string:
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+ "allwinner,sun8i-a83t-emac"
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+ "allwinner,sun8i-h3-emac"
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+ "allwinner,sun50i-a64-emac"
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+- reg: address and length of the register for the device.
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+- interrupts: interrupt for the device
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+- interrupt-names: should be "macirq"
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+- clocks: A phandle to the reference clock for this device
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+- clock-names: should be "stmmaceth"
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+- resets: A phandle to the reset control for this device
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+- reset-names: should be "stmmaceth"
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+- phy-mode: See ethernet.txt
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+- phy-handle: See ethernet.txt
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+- #address-cells: shall be 1
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+- #size-cells: shall be 0
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+- syscon: A phandle to the syscon of the SoC with one of the following
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+ compatible string:
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+ - allwinner,sun8i-h3-system-controller
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+ - allwinner,sun50i-a64-system-controller
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+ - allwinner,sun8i-a83t-system-controller
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+
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+Optional properties:
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+- allwinner,tx-delay-ps: TX clock delay chain value in ps. Range value is 0-700. Default is 0)
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+- allwinner,rx-delay-ps: RX clock delay chain value in ps. Range value is 0-3100. Default is 0)
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+Both delay properties need to be a multiple of 100. They control the delay for
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+external PHY.
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+
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+Optional properties for "allwinner,sun8i-h3-emac":
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+- allwinner,leds-active-low: EPHY LEDs are active low
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+
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+Required child node of emac:
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+- mdio bus node: should be named mdio
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+
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+Required properties of the mdio node:
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+- #address-cells: shall be 1
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+- #size-cells: shall be 0
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+
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+The device node referenced by "phy" or "phy-handle" should be a child node
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+of the mdio node. See phy.txt for the generic PHY bindings.
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+
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+Required properties of the phy node with "allwinner,sun8i-h3-emac":
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+- clocks: a phandle to the reference clock for the EPHY
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+- resets: a phandle to the reset control for the EPHY
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+
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+Example:
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+
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+emac: ethernet@1c0b000 {
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+ compatible = "allwinner,sun8i-h3-emac";
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+ syscon = <&syscon>;
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+ reg = <0x01c0b000 0x104>;
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+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+ resets = <&ccu RST_BUS_EMAC>;
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+ reset-names = "stmmaceth";
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+ clocks = <&ccu CLK_BUS_EMAC>;
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+ clock-names = "stmmaceth";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ phy-handle = <&int_mii_phy>;
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+ phy-mode = "mii";
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+ allwinner,leds-active-low;
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+ mdio: mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ int_mii_phy: ethernet-phy@1 {
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+ reg = <1>;
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+ clocks = <&ccu CLK_BUS_EPHY>;
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+ resets = <&ccu RST_BUS_EPHY>;
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+ };
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+ };
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+};
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