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@@ -270,30 +270,28 @@ static ssize_t amdgpu_set_pp_force_state(struct device *dev,
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struct drm_device *ddev = dev_get_drvdata(dev);
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struct amdgpu_device *adev = ddev->dev_private;
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enum amd_pm_state_type state = 0;
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- long idx;
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+ unsigned long idx;
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int ret;
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if (strlen(buf) == 1)
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adev->pp_force_state_enabled = false;
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- else {
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- ret = kstrtol(buf, 0, &idx);
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+ else if (adev->pp_enabled) {
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+ struct pp_states_info data;
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- if (ret) {
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+ ret = kstrtoul(buf, 0, &idx);
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+ if (ret || idx >= ARRAY_SIZE(data.states)) {
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count = -EINVAL;
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goto fail;
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}
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- if (adev->pp_enabled) {
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- struct pp_states_info data;
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- amdgpu_dpm_get_pp_num_states(adev, &data);
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- state = data.states[idx];
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- /* only set user selected power states */
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- if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
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- state != POWER_STATE_TYPE_DEFAULT) {
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- amdgpu_dpm_dispatch_task(adev,
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- AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
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- adev->pp_force_state_enabled = true;
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- }
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+ amdgpu_dpm_get_pp_num_states(adev, &data);
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+ state = data.states[idx];
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+ /* only set user selected power states */
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+ if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
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+ state != POWER_STATE_TYPE_DEFAULT) {
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+ amdgpu_dpm_dispatch_task(adev,
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+ AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
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+ adev->pp_force_state_enabled = true;
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}
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}
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fail:
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