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@@ -30,6 +30,7 @@
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#include <dt-bindings/thermal/tegra124-soctherm.h>
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+#include "../thermal_core.h"
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#include "soctherm.h"
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#define SENSOR_CONFIG0 0
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@@ -67,35 +68,228 @@
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#define READBACK_ADD_HALF BIT(7)
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#define READBACK_NEGATE BIT(0)
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+/*
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+ * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h
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+ * because it will be used by tegraxxx_soctherm.c
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+ */
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+#define THERMCTL_LVL0_CPU0_EN_MASK BIT(8)
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+#define THERMCTL_LVL0_CPU0_CPU_THROT_MASK (0x3 << 5)
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+#define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1
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+#define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2
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+#define THERMCTL_LVL0_CPU0_GPU_THROT_MASK (0x3 << 3)
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+#define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT 0x1
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+#define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY 0x2
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+#define THERMCTL_LVL0_CPU0_MEM_THROT_MASK BIT(2)
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+#define THERMCTL_LVL0_CPU0_STATUS_MASK 0x3
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+
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+#define THERMCTL_LVL0_UP_STATS 0x10
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+#define THERMCTL_LVL0_DN_STATS 0x14
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+
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+#define THERMCTL_STATS_CTL 0x94
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+#define STATS_CTL_CLR_DN 0x8
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+#define STATS_CTL_EN_DN 0x4
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+#define STATS_CTL_CLR_UP 0x2
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+#define STATS_CTL_EN_UP 0x1
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+
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+#define THROT_GLOBAL_CFG 0x400
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+#define THROT_GLOBAL_ENB_MASK BIT(0)
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+
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+#define CPU_PSKIP_STATUS 0x418
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+#define XPU_PSKIP_STATUS_M_MASK (0xff << 12)
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+#define XPU_PSKIP_STATUS_N_MASK (0xff << 4)
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+#define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK BIT(1)
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+#define XPU_PSKIP_STATUS_ENABLED_MASK BIT(0)
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+
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+#define THROT_PRIORITY_LOCK 0x424
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+#define THROT_PRIORITY_LOCK_PRIORITY_MASK 0xff
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+
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+#define THROT_STATUS 0x428
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+#define THROT_STATUS_BREACH_MASK BIT(12)
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+#define THROT_STATUS_STATE_MASK (0xff << 4)
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+#define THROT_STATUS_ENABLED_MASK BIT(0)
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+
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+#define THROT_PSKIP_CTRL_LITE_CPU 0x430
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+#define THROT_PSKIP_CTRL_ENABLE_MASK BIT(31)
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+#define THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
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+#define THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
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+#define THROT_PSKIP_CTRL_VECT_GPU_MASK (0x7 << 16)
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+#define THROT_PSKIP_CTRL_VECT_CPU_MASK (0x7 << 8)
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+#define THROT_PSKIP_CTRL_VECT2_CPU_MASK 0x7
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+
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+#define THROT_VECT_NONE 0x0 /* 3'b000 */
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+#define THROT_VECT_LOW 0x1 /* 3'b001 */
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+#define THROT_VECT_MED 0x3 /* 3'b011 */
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+#define THROT_VECT_HIGH 0x7 /* 3'b111 */
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+
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+#define THROT_PSKIP_RAMP_LITE_CPU 0x434
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+#define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
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+#define THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
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+#define THROT_PSKIP_RAMP_STEP_MASK 0xff
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+
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+#define THROT_PRIORITY_LITE 0x444
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+#define THROT_PRIORITY_LITE_PRIO_MASK 0xff
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+
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+#define THROT_DELAY_LITE 0x448
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+#define THROT_DELAY_LITE_DELAY_MASK 0xff
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+
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+/* car register offsets needed for enabling HW throttling */
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+#define CAR_SUPER_CCLKG_DIVIDER 0x36c
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+#define CDIVG_USE_THERM_CONTROLS_MASK BIT(30)
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+
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+/* ccroc register offsets needed for enabling HW throttling for Tegra132 */
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+#define CCROC_SUPER_CCLKG_DIVIDER 0x024
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+
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+#define CCROC_GLOBAL_CFG 0x148
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+
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+#define CCROC_THROT_PSKIP_RAMP_CPU 0x150
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+#define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31)
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+#define CCROC_THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8)
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+#define CCROC_THROT_PSKIP_RAMP_STEP_MASK 0xff
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+
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+#define CCROC_THROT_PSKIP_CTRL_CPU 0x154
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+#define CCROC_THROT_PSKIP_CTRL_ENB_MASK BIT(31)
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+#define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8)
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+#define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK 0xff
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+
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/* get val from register(r) mask bits(m) */
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#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
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/* set val(v) to mask bits(m) of register(r) */
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#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
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(((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
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+/* get dividend from the depth */
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+#define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
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+
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+/* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
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+#define THROT_OFFSET 0x30
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+#define THROT_PSKIP_CTRL(throt, dev) (THROT_PSKIP_CTRL_LITE_CPU + \
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+ (THROT_OFFSET * throt) + (8 * dev))
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+#define THROT_PSKIP_RAMP(throt, dev) (THROT_PSKIP_RAMP_LITE_CPU + \
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+ (THROT_OFFSET * throt) + (8 * dev))
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+
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+/* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */
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+#define THROT_PRIORITY_CTRL(throt) (THROT_PRIORITY_LITE + \
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+ (THROT_OFFSET * throt))
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+#define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \
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+ (THROT_OFFSET * throt))
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+
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+/* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
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+#define CCROC_THROT_OFFSET 0x0c
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+#define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \
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+ (CCROC_THROT_OFFSET * vect))
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+#define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect) (CCROC_THROT_PSKIP_RAMP_CPU + \
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+ (CCROC_THROT_OFFSET * vect))
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+
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+/* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */
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+#define THERMCTL_LVL_REGS_SIZE 0x20
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+#define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
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+
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static const int min_low_temp = -127000;
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static const int max_high_temp = 127000;
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+enum soctherm_throttle_id {
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+ THROTTLE_LIGHT = 0,
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+ THROTTLE_HEAVY,
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+ THROTTLE_SIZE,
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+};
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+
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+enum soctherm_throttle_dev_id {
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+ THROTTLE_DEV_CPU = 0,
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+ THROTTLE_DEV_GPU,
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+ THROTTLE_DEV_SIZE,
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+};
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+
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+static const char *const throt_names[] = {
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+ [THROTTLE_LIGHT] = "light",
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+ [THROTTLE_HEAVY] = "heavy",
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+};
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+
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+struct tegra_soctherm;
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struct tegra_thermctl_zone {
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void __iomem *reg;
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struct device *dev;
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+ struct tegra_soctherm *ts;
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struct thermal_zone_device *tz;
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const struct tegra_tsensor_group *sg;
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};
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+struct soctherm_throt_cfg {
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+ const char *name;
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+ unsigned int id;
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+ u8 priority;
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+ u8 cpu_throt_level;
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+ u32 cpu_throt_depth;
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+ struct thermal_cooling_device *cdev;
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+ bool init;
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+};
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+
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struct tegra_soctherm {
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struct reset_control *reset;
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struct clk *clock_tsensor;
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struct clk *clock_soctherm;
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void __iomem *regs;
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- struct thermal_zone_device **thermctl_tzs;
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+ void __iomem *clk_regs;
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+ void __iomem *ccroc_regs;
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u32 *calib;
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+ struct thermal_zone_device **thermctl_tzs;
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struct tegra_soctherm_soc *soc;
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+ struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
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+
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struct dentry *debugfs_dir;
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};
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+/**
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+ * clk_writel() - writes a value to a CAR register
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+ * @ts: pointer to a struct tegra_soctherm
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+ * @v: the value to write
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+ * @reg: the register offset
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+ *
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+ * Writes @v to @reg. No return value.
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+ */
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+static inline void clk_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
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+{
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+ writel(value, (ts->clk_regs + reg));
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+}
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+
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+/**
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+ * clk_readl() - reads specified register from CAR IP block
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+ * @ts: pointer to a struct tegra_soctherm
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+ * @reg: register address to be read
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+ *
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+ * Return: the value of the register
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+ */
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+static inline u32 clk_readl(struct tegra_soctherm *ts, u32 reg)
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+{
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+ return readl(ts->clk_regs + reg);
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+}
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+
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+/**
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+ * ccroc_writel() - writes a value to a CCROC register
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+ * @ts: pointer to a struct tegra_soctherm
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+ * @v: the value to write
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+ * @reg: the register offset
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+ *
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+ * Writes @v to @reg. No return value.
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+ */
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+static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
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+{
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+ writel(value, (ts->ccroc_regs + reg));
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+}
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+
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+/**
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+ * ccroc_readl() - reads specified register from CCROC IP block
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+ * @ts: pointer to a struct tegra_soctherm
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+ * @reg: register address to be read
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+ *
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+ * Return: the value of the register
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+ */
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+static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg)
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+{
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+ return readl(ts->ccroc_regs + reg);
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+}
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+
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static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i)
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{
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const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
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@@ -150,11 +344,17 @@ static int tegra_thermctl_get_temp(void *data, int *out_temp)
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static int
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thermtrip_program(struct device *dev, const struct tegra_tsensor_group *sg,
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int trip_temp);
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+static int
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+throttrip_program(struct device *dev, const struct tegra_tsensor_group *sg,
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+ struct soctherm_throt_cfg *stc, int trip_temp);
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+static struct soctherm_throt_cfg *
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+find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name);
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static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
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{
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struct tegra_thermctl_zone *zone = data;
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struct thermal_zone_device *tz = zone->tz;
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+ struct tegra_soctherm *ts = zone->ts;
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const struct tegra_tsensor_group *sg = zone->sg;
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struct device *dev = zone->dev;
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enum thermal_trip_type type;
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@@ -167,10 +367,29 @@ static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
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if (ret)
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return ret;
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- if (type != THERMAL_TRIP_CRITICAL)
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- return 0;
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+ if (type == THERMAL_TRIP_CRITICAL) {
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+ return thermtrip_program(dev, sg, temp);
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+ } else if (type == THERMAL_TRIP_HOT) {
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+ int i;
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+
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+ for (i = 0; i < THROTTLE_SIZE; i++) {
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+ struct thermal_cooling_device *cdev;
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+ struct soctherm_throt_cfg *stc;
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+
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+ if (!ts->throt_cfgs[i].init)
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+ continue;
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+
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+ cdev = ts->throt_cfgs[i].cdev;
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+ if (get_thermal_instance(tz, cdev, trip))
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+ stc = find_throttle_cfg_by_name(ts, cdev->type);
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+ else
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+ continue;
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+
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+ return throttrip_program(dev, sg, stc, temp);
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+ }
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+ }
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- return thermtrip_program(dev, sg, temp);
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+ return 0;
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}
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static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
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@@ -237,15 +456,111 @@ static int thermtrip_program(struct device *dev,
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return 0;
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}
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+/**
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+ * throttrip_program() - Configures the hardware to throttle the
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+ * pulse if a given sensor group reaches a given temperature
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+ * @dev: ptr to the struct device for the SOC_THERM IP block
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+ * @sg: pointer to the sensor group to set the thermtrip temperature for
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+ * @stc: pointer to the throttle need to be triggered
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+ * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
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+ *
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+ * Sets the thermal trip threshold and throttle event of the given sensor
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+ * group. If this threshold is crossed, the hardware will trigger the
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+ * throttle.
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+ *
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+ * Note that, although @trip_temp is specified in millicelsius, the
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+ * hardware is programmed in degrees Celsius.
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+ *
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+ * Return: 0 upon success, or %-EINVAL upon failure.
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+ */
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+static int throttrip_program(struct device *dev,
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+ const struct tegra_tsensor_group *sg,
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+ struct soctherm_throt_cfg *stc,
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+ int trip_temp)
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+{
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+ struct tegra_soctherm *ts = dev_get_drvdata(dev);
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+ int temp, cpu_throt, gpu_throt;
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+ unsigned int throt;
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+ u32 r, reg_off;
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+
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+ if (!dev || !sg || !stc || !stc->init)
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+ return -EINVAL;
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+
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+ temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
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+
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+ /* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */
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+ throt = stc->id;
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+ reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
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+
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+ if (throt == THROTTLE_LIGHT) {
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+ cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT;
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+ gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT;
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+ } else {
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+ cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY;
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+ gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY;
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+ if (throt != THROTTLE_HEAVY)
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+ dev_warn(dev,
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+ "invalid throt id %d - assuming HEAVY",
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+ throt);
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+ }
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+
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+ r = readl(ts->regs + reg_off);
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+ r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
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+ r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
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+ r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
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+ r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
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+ r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
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+ writel(r, ts->regs + reg_off);
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+
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+ return 0;
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+}
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+
|
|
|
+static struct soctherm_throt_cfg *
|
|
|
+find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
|
|
|
+{
|
|
|
+ unsigned int i;
|
|
|
+
|
|
|
+ for (i = 0; ts->throt_cfgs[i].name; i++)
|
|
|
+ if (!strcmp(ts->throt_cfgs[i].name, name))
|
|
|
+ return &ts->throt_cfgs[i];
|
|
|
+
|
|
|
+ return NULL;
|
|
|
+}
|
|
|
+
|
|
|
+static int get_hot_temp(struct thermal_zone_device *tz, int *trip, int *temp)
|
|
|
+{
|
|
|
+ int ntrips, i, ret;
|
|
|
+ enum thermal_trip_type type;
|
|
|
+
|
|
|
+ ntrips = of_thermal_get_ntrips(tz);
|
|
|
+ if (ntrips <= 0)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ for (i = 0; i < ntrips; i++) {
|
|
|
+ ret = tz->ops->get_trip_type(tz, i, &type);
|
|
|
+ if (ret)
|
|
|
+ return -EINVAL;
|
|
|
+ if (type == THERMAL_TRIP_HOT) {
|
|
|
+ ret = tz->ops->get_trip_temp(tz, i, temp);
|
|
|
+ if (!ret)
|
|
|
+ *trip = i;
|
|
|
+
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ return -EINVAL;
|
|
|
+}
|
|
|
+
|
|
|
/**
|
|
|
* tegra_soctherm_set_hwtrips() - set HW trip point from DT data
|
|
|
* @dev: struct device * of the SOC_THERM instance
|
|
|
*
|
|
|
* Configure the SOC_THERM HW trip points, setting "THERMTRIP"
|
|
|
- * trip points , using "critical" type trip_temp from thermal
|
|
|
- * zone.
|
|
|
- * After they have been configured, THERMTRIP will take action
|
|
|
- * when the configured SoC thermal sensor group reaches a
|
|
|
+ * "THROTTLE" trip points , using "critical" or "hot" type trip_temp
|
|
|
+ * from thermal zone.
|
|
|
+ * After they have been configured, THERMTRIP or THROTTLE will take
|
|
|
+ * action when the configured SoC thermal sensor group reaches a
|
|
|
* certain temperature.
|
|
|
*
|
|
|
* Return: 0 upon success, or a negative error code on failure.
|
|
|
@@ -254,19 +569,24 @@ static int thermtrip_program(struct device *dev,
|
|
|
* THERMTRIP has been enabled successfully when a message similar to
|
|
|
* this one appears on the serial console:
|
|
|
* "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
|
|
|
+ * THROTTLE has been enabled successfully when a message similar to
|
|
|
+ * this one appears on the serial console:
|
|
|
+ * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
|
|
|
*/
|
|
|
static int tegra_soctherm_set_hwtrips(struct device *dev,
|
|
|
const struct tegra_tsensor_group *sg,
|
|
|
struct thermal_zone_device *tz)
|
|
|
{
|
|
|
- int temperature;
|
|
|
+ struct tegra_soctherm *ts = dev_get_drvdata(dev);
|
|
|
+ struct soctherm_throt_cfg *stc;
|
|
|
+ int i, trip, temperature;
|
|
|
int ret;
|
|
|
|
|
|
ret = tz->ops->get_crit_temp(tz, &temperature);
|
|
|
if (ret) {
|
|
|
dev_warn(dev, "thermtrip: %s: missing critical temperature\n",
|
|
|
sg->name);
|
|
|
- return ret;
|
|
|
+ goto set_throttle;
|
|
|
}
|
|
|
|
|
|
ret = thermtrip_program(dev, sg, temperature);
|
|
|
@@ -280,6 +600,43 @@ static int tegra_soctherm_set_hwtrips(struct device *dev,
|
|
|
"thermtrip: will shut down when %s reaches %d mC\n",
|
|
|
sg->name, temperature);
|
|
|
|
|
|
+set_throttle:
|
|
|
+ ret = get_hot_temp(tz, &trip, &temperature);
|
|
|
+ if (ret) {
|
|
|
+ dev_warn(dev, "throttrip: %s: missing hot temperature\n",
|
|
|
+ sg->name);
|
|
|
+ return 0;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < THROTTLE_SIZE; i++) {
|
|
|
+ struct thermal_cooling_device *cdev;
|
|
|
+
|
|
|
+ if (!ts->throt_cfgs[i].init)
|
|
|
+ continue;
|
|
|
+
|
|
|
+ cdev = ts->throt_cfgs[i].cdev;
|
|
|
+ if (get_thermal_instance(tz, cdev, trip))
|
|
|
+ stc = find_throttle_cfg_by_name(ts, cdev->type);
|
|
|
+ else
|
|
|
+ continue;
|
|
|
+
|
|
|
+ ret = throttrip_program(dev, sg, stc, temperature);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "throttrip: %s: error during enable\n",
|
|
|
+ sg->name);
|
|
|
+ return ret;
|
|
|
+ }
|
|
|
+
|
|
|
+ dev_info(dev,
|
|
|
+ "throttrip: will throttle when %s reaches %d mC\n",
|
|
|
+ sg->name, temperature);
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (i == THROTTLE_SIZE)
|
|
|
+ dev_warn(dev, "throttrip: %s: missing throttle cdev\n",
|
|
|
+ sg->name);
|
|
|
+
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
@@ -291,7 +648,7 @@ static int regs_show(struct seq_file *s, void *data)
|
|
|
const struct tegra_tsensor *tsensors = ts->soc->tsensors;
|
|
|
const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;
|
|
|
u32 r, state;
|
|
|
- int i;
|
|
|
+ int i, level;
|
|
|
|
|
|
seq_puts(s, "-----TSENSE (convert HW)-----\n");
|
|
|
|
|
|
@@ -365,6 +722,81 @@ static int regs_show(struct seq_file *s, void *data)
|
|
|
state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
|
|
|
seq_printf(s, " MEM(%d)\n", translate_temp(state));
|
|
|
|
|
|
+ for (i = 0; i < ts->soc->num_ttgs; i++) {
|
|
|
+ seq_printf(s, "%s:\n", ttgs[i]->name);
|
|
|
+ for (level = 0; level < 4; level++) {
|
|
|
+ s32 v;
|
|
|
+ u32 mask;
|
|
|
+ u16 off = ttgs[i]->thermctl_lvl0_offset;
|
|
|
+
|
|
|
+ r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
|
|
|
+
|
|
|
+ mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;
|
|
|
+ state = REG_GET_MASK(r, mask);
|
|
|
+ v = sign_extend32(state, ts->soc->bptt - 1);
|
|
|
+ v *= ts->soc->thresh_grain;
|
|
|
+ seq_printf(s, " %d: Up/Dn(%d /", level, v);
|
|
|
+
|
|
|
+ mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;
|
|
|
+ state = REG_GET_MASK(r, mask);
|
|
|
+ v = sign_extend32(state, ts->soc->bptt - 1);
|
|
|
+ v *= ts->soc->thresh_grain;
|
|
|
+ seq_printf(s, "%d ) ", v);
|
|
|
+
|
|
|
+ mask = THERMCTL_LVL0_CPU0_EN_MASK;
|
|
|
+ state = REG_GET_MASK(r, mask);
|
|
|
+ seq_printf(s, "En(%d) ", state);
|
|
|
+
|
|
|
+ mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK;
|
|
|
+ state = REG_GET_MASK(r, mask);
|
|
|
+ seq_puts(s, "CPU Throt");
|
|
|
+ if (!state)
|
|
|
+ seq_printf(s, "(%s) ", "none");
|
|
|
+ else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT)
|
|
|
+ seq_printf(s, "(%s) ", "L");
|
|
|
+ else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY)
|
|
|
+ seq_printf(s, "(%s) ", "H");
|
|
|
+ else
|
|
|
+ seq_printf(s, "(%s) ", "H+L");
|
|
|
+
|
|
|
+ mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK;
|
|
|
+ state = REG_GET_MASK(r, mask);
|
|
|
+ seq_puts(s, "GPU Throt");
|
|
|
+ if (!state)
|
|
|
+ seq_printf(s, "(%s) ", "none");
|
|
|
+ else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT)
|
|
|
+ seq_printf(s, "(%s) ", "L");
|
|
|
+ else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY)
|
|
|
+ seq_printf(s, "(%s) ", "H");
|
|
|
+ else
|
|
|
+ seq_printf(s, "(%s) ", "H+L");
|
|
|
+
|
|
|
+ mask = THERMCTL_LVL0_CPU0_STATUS_MASK;
|
|
|
+ state = REG_GET_MASK(r, mask);
|
|
|
+ seq_printf(s, "Status(%s)\n",
|
|
|
+ state == 0 ? "LO" :
|
|
|
+ state == 1 ? "In" :
|
|
|
+ state == 2 ? "Res" : "HI");
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ r = readl(ts->regs + THERMCTL_STATS_CTL);
|
|
|
+ seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
|
|
|
+ r & STATS_CTL_EN_UP ? "En" : "--",
|
|
|
+ r & STATS_CTL_EN_DN ? "En" : "--");
|
|
|
+
|
|
|
+ for (level = 0; level < 4; level++) {
|
|
|
+ u16 off;
|
|
|
+
|
|
|
+ off = THERMCTL_LVL0_UP_STATS;
|
|
|
+ r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
|
|
|
+ seq_printf(s, " Level_%d Up(%d) ", level, r);
|
|
|
+
|
|
|
+ off = THERMCTL_LVL0_DN_STATS;
|
|
|
+ r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
|
|
|
+ seq_printf(s, "Dn(%d)\n", r);
|
|
|
+ }
|
|
|
+
|
|
|
r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
|
|
|
state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);
|
|
|
seq_printf(s, "Thermtrip Any En(%d)\n", state);
|
|
|
@@ -376,6 +808,32 @@ static int regs_show(struct seq_file *s, void *data)
|
|
|
seq_printf(s, "Thresh(%d)\n", state);
|
|
|
}
|
|
|
|
|
|
+ r = readl(ts->regs + THROT_GLOBAL_CFG);
|
|
|
+ seq_puts(s, "\n");
|
|
|
+ seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
|
|
|
+
|
|
|
+ seq_puts(s, "---------------------------------------------------\n");
|
|
|
+ r = readl(ts->regs + THROT_STATUS);
|
|
|
+ state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);
|
|
|
+ seq_printf(s, "THROT STATUS: breach(%d) ", state);
|
|
|
+ state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);
|
|
|
+ seq_printf(s, "state(%d) ", state);
|
|
|
+ state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);
|
|
|
+ seq_printf(s, "enabled(%d)\n", state);
|
|
|
+
|
|
|
+ r = readl(ts->regs + CPU_PSKIP_STATUS);
|
|
|
+ if (ts->soc->use_ccroc) {
|
|
|
+ state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
|
|
|
+ seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state);
|
|
|
+ } else {
|
|
|
+ state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);
|
|
|
+ seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state);
|
|
|
+ state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);
|
|
|
+ seq_printf(s, "N(%d) ", state);
|
|
|
+ state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
|
|
|
+ seq_printf(s, "enabled(%d)\n", state);
|
|
|
+ }
|
|
|
+
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
@@ -449,6 +907,326 @@ static int soctherm_clk_enable(struct platform_device *pdev, bool enable)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev,
|
|
|
+ unsigned long *max_state)
|
|
|
+{
|
|
|
+ *max_state = 1;
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev,
|
|
|
+ unsigned long *cur_state)
|
|
|
+{
|
|
|
+ struct tegra_soctherm *ts = cdev->devdata;
|
|
|
+ u32 r;
|
|
|
+
|
|
|
+ r = readl(ts->regs + THROT_STATUS);
|
|
|
+ if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))
|
|
|
+ *cur_state = 1;
|
|
|
+ else
|
|
|
+ *cur_state = 0;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int throt_set_cdev_state(struct thermal_cooling_device *cdev,
|
|
|
+ unsigned long cur_state)
|
|
|
+{
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static struct thermal_cooling_device_ops throt_cooling_ops = {
|
|
|
+ .get_max_state = throt_get_cdev_max_state,
|
|
|
+ .get_cur_state = throt_get_cdev_cur_state,
|
|
|
+ .set_cur_state = throt_set_cdev_state,
|
|
|
+};
|
|
|
+
|
|
|
+/**
|
|
|
+ * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
|
|
|
+ * and register them as cooling devices.
|
|
|
+ */
|
|
|
+static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct tegra_soctherm *ts = dev_get_drvdata(dev);
|
|
|
+ struct device_node *np_stc, *np_stcc;
|
|
|
+ const char *name;
|
|
|
+ u32 val;
|
|
|
+ int i, r;
|
|
|
+
|
|
|
+ for (i = 0; i < THROTTLE_SIZE; i++) {
|
|
|
+ ts->throt_cfgs[i].name = throt_names[i];
|
|
|
+ ts->throt_cfgs[i].id = i;
|
|
|
+ ts->throt_cfgs[i].init = false;
|
|
|
+ }
|
|
|
+
|
|
|
+ np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");
|
|
|
+ if (!np_stc) {
|
|
|
+ dev_info(dev,
|
|
|
+ "throttle-cfg: no throttle-cfgs - not enabling\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ for_each_child_of_node(np_stc, np_stcc) {
|
|
|
+ struct soctherm_throt_cfg *stc;
|
|
|
+ struct thermal_cooling_device *tcd;
|
|
|
+
|
|
|
+ name = np_stcc->name;
|
|
|
+ stc = find_throttle_cfg_by_name(ts, name);
|
|
|
+ if (!stc) {
|
|
|
+ dev_err(dev,
|
|
|
+ "throttle-cfg: could not find %s\n", name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ r = of_property_read_u32(np_stcc, "nvidia,priority", &val);
|
|
|
+ if (r) {
|
|
|
+ dev_info(dev,
|
|
|
+ "throttle-cfg: %s: missing priority\n", name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ stc->priority = val;
|
|
|
+
|
|
|
+ if (ts->soc->use_ccroc) {
|
|
|
+ r = of_property_read_u32(np_stcc,
|
|
|
+ "nvidia,cpu-throt-level",
|
|
|
+ &val);
|
|
|
+ if (r) {
|
|
|
+ dev_info(dev,
|
|
|
+ "throttle-cfg: %s: missing cpu-throt-level\n",
|
|
|
+ name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ stc->cpu_throt_level = val;
|
|
|
+ } else {
|
|
|
+ r = of_property_read_u32(np_stcc,
|
|
|
+ "nvidia,cpu-throt-percent",
|
|
|
+ &val);
|
|
|
+ if (r) {
|
|
|
+ dev_info(dev,
|
|
|
+ "throttle-cfg: %s: missing cpu-throt-percent\n",
|
|
|
+ name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+ stc->cpu_throt_depth = val;
|
|
|
+ }
|
|
|
+
|
|
|
+ tcd = thermal_of_cooling_device_register(np_stcc,
|
|
|
+ (char *)name, ts,
|
|
|
+ &throt_cooling_ops);
|
|
|
+ of_node_put(np_stcc);
|
|
|
+ if (IS_ERR_OR_NULL(tcd)) {
|
|
|
+ dev_err(dev,
|
|
|
+ "throttle-cfg: %s: failed to register cooling device\n",
|
|
|
+ name);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ stc->cdev = tcd;
|
|
|
+ stc->init = true;
|
|
|
+ }
|
|
|
+
|
|
|
+ of_node_put(np_stc);
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
|
|
|
+ * @level: describing the level LOW/MED/HIGH of throttling
|
|
|
+ *
|
|
|
+ * It's necessary to set up the CPU-local CCROC NV_THERM instance with
|
|
|
+ * the M/N values desired for each level. This function does this.
|
|
|
+ *
|
|
|
+ * This function pre-programs the CCROC NV_THERM levels in terms of
|
|
|
+ * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
|
|
|
+ * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY.
|
|
|
+ */
|
|
|
+static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level)
|
|
|
+{
|
|
|
+ u8 depth, dividend;
|
|
|
+ u32 r;
|
|
|
+
|
|
|
+ switch (level) {
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
|
|
|
+ depth = 50;
|
|
|
+ break;
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_MED:
|
|
|
+ depth = 75;
|
|
|
+ break;
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
|
|
|
+ depth = 80;
|
|
|
+ break;
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_NONE:
|
|
|
+ return;
|
|
|
+ default:
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ dividend = THROT_DEPTH_DIVIDEND(depth);
|
|
|
+
|
|
|
+ /* setup PSKIP in ccroc nv_therm registers */
|
|
|
+ r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
|
|
|
+ r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
|
|
|
+ r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
|
|
|
+ ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
|
|
|
+
|
|
|
+ r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
|
|
|
+ r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
|
|
|
+ r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
|
|
|
+ r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
|
|
|
+ ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * throttlectl_cpu_level_select() - program CPU pulse skipper config
|
|
|
+ * @throt: the LIGHT/HEAVY of throttle event id
|
|
|
+ *
|
|
|
+ * Pulse skippers are used to throttle clock frequencies. This
|
|
|
+ * function programs the pulse skippers based on @throt and platform
|
|
|
+ * data. This function is used on SoCs which have CPU-local pulse
|
|
|
+ * skipper control, such as T13x. It programs soctherm's interface to
|
|
|
+ * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling
|
|
|
+ * vectors. PSKIP_BYPASS mode is set as required per HW spec.
|
|
|
+ */
|
|
|
+static void throttlectl_cpu_level_select(struct tegra_soctherm *ts,
|
|
|
+ enum soctherm_throttle_id throt)
|
|
|
+{
|
|
|
+ u32 r, throt_vect;
|
|
|
+
|
|
|
+ /* Denver:CCROC NV_THERM interface N:3 Mapping */
|
|
|
+ switch (ts->throt_cfgs[throt].cpu_throt_level) {
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
|
|
|
+ throt_vect = THROT_VECT_LOW;
|
|
|
+ break;
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_MED:
|
|
|
+ throt_vect = THROT_VECT_MED;
|
|
|
+ break;
|
|
|
+ case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
|
|
|
+ throt_vect = THROT_VECT_HIGH;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ throt_vect = THROT_VECT_NONE;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
|
|
|
+ writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
|
|
|
+
|
|
|
+ /* bypass sequencer in soc_therm as it is programmed in ccroc */
|
|
|
+ r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
|
|
|
+ writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * throttlectl_cpu_mn() - program CPU pulse skipper configuration
|
|
|
+ * @throt: the LIGHT/HEAVY of throttle event id
|
|
|
+ *
|
|
|
+ * Pulse skippers are used to throttle clock frequencies. This
|
|
|
+ * function programs the pulse skippers based on @throt and platform
|
|
|
+ * data. This function is used for CPUs that have "remote" pulse
|
|
|
+ * skipper control, e.g., the CPU pulse skipper is controlled by the
|
|
|
+ * SOC_THERM IP block. (SOC_THERM is located outside the CPU
|
|
|
+ * complex.)
|
|
|
+ */
|
|
|
+static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
|
|
|
+ enum soctherm_throttle_id throt)
|
|
|
+{
|
|
|
+ u32 r;
|
|
|
+ int depth;
|
|
|
+ u8 dividend;
|
|
|
+
|
|
|
+ depth = ts->throt_cfgs[throt].cpu_throt_depth;
|
|
|
+ dividend = THROT_DEPTH_DIVIDEND(depth);
|
|
|
+
|
|
|
+ r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
|
|
|
+ writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
|
|
|
+
|
|
|
+ r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
|
|
|
+ r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
|
|
|
+ writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * soctherm_throttle_program() - programs pulse skippers' configuration
|
|
|
+ * @throt: the LIGHT/HEAVY of the throttle event id.
|
|
|
+ *
|
|
|
+ * Pulse skippers are used to throttle clock frequencies.
|
|
|
+ * This function programs the pulse skippers.
|
|
|
+ */
|
|
|
+static void soctherm_throttle_program(struct tegra_soctherm *ts,
|
|
|
+ enum soctherm_throttle_id throt)
|
|
|
+{
|
|
|
+ u32 r;
|
|
|
+ struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];
|
|
|
+
|
|
|
+ if (!stc.init)
|
|
|
+ return;
|
|
|
+
|
|
|
+ /* Setup PSKIP parameters */
|
|
|
+ if (ts->soc->use_ccroc)
|
|
|
+ throttlectl_cpu_level_select(ts, throt);
|
|
|
+ else
|
|
|
+ throttlectl_cpu_mn(ts, throt);
|
|
|
+
|
|
|
+ r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
|
|
|
+ writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
|
|
|
+
|
|
|
+ r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
|
|
|
+ writel(r, ts->regs + THROT_DELAY_CTRL(throt));
|
|
|
+
|
|
|
+ r = readl(ts->regs + THROT_PRIORITY_LOCK);
|
|
|
+ r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);
|
|
|
+ if (r >= stc.priority)
|
|
|
+ return;
|
|
|
+ r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
|
|
|
+ stc.priority);
|
|
|
+ writel(r, ts->regs + THROT_PRIORITY_LOCK);
|
|
|
+}
|
|
|
+
|
|
|
+static void tegra_soctherm_throttle(struct device *dev)
|
|
|
+{
|
|
|
+ struct tegra_soctherm *ts = dev_get_drvdata(dev);
|
|
|
+ u32 v;
|
|
|
+ int i;
|
|
|
+
|
|
|
+ /* configure LOW, MED and HIGH levels for CCROC NV_THERM */
|
|
|
+ if (ts->soc->use_ccroc) {
|
|
|
+ throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW);
|
|
|
+ throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED);
|
|
|
+ throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Thermal HW throttle programming */
|
|
|
+ for (i = 0; i < THROTTLE_SIZE; i++)
|
|
|
+ soctherm_throttle_program(ts, i);
|
|
|
+
|
|
|
+ v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
|
|
|
+ if (ts->soc->use_ccroc) {
|
|
|
+ ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
|
|
|
+
|
|
|
+ v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
|
|
|
+ v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
|
|
|
+ ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
|
|
|
+ } else {
|
|
|
+ writel(v, ts->regs + THROT_GLOBAL_CFG);
|
|
|
+
|
|
|
+ v = clk_readl(ts, CAR_SUPER_CCLKG_DIVIDER);
|
|
|
+ v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
|
|
|
+ clk_writel(ts, v, CAR_SUPER_CCLKG_DIVIDER);
|
|
|
+ }
|
|
|
+
|
|
|
+ /* initialize stats collection */
|
|
|
+ v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
|
|
|
+ STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
|
|
|
+ writel(v, ts->regs + THERMCTL_STATS_CTL);
|
|
|
+}
|
|
|
+
|
|
|
static void soctherm_init(struct platform_device *pdev)
|
|
|
{
|
|
|
struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
|
|
|
@@ -475,6 +1253,9 @@ static void soctherm_init(struct platform_device *pdev)
|
|
|
}
|
|
|
writel(pdiv, tegra->regs + SENSOR_PDIV);
|
|
|
writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
|
|
|
+
|
|
|
+ /* Configure hw throttle */
|
|
|
+ tegra_soctherm_throttle(&pdev->dev);
|
|
|
}
|
|
|
|
|
|
static const struct of_device_id tegra_soctherm_of_match[] = {
|
|
|
@@ -527,10 +1308,31 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
|
|
|
|
|
|
tegra->soc = soc;
|
|
|
|
|
|
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
|
+ "soctherm-reg");
|
|
|
tegra->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
|
- if (IS_ERR(tegra->regs))
|
|
|
+ if (IS_ERR(tegra->regs)) {
|
|
|
+ dev_err(&pdev->dev, "can't get soctherm registers");
|
|
|
return PTR_ERR(tegra->regs);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!tegra->soc->use_ccroc) {
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
|
+ "car-reg");
|
|
|
+ tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res);
|
|
|
+ if (IS_ERR(tegra->clk_regs)) {
|
|
|
+ dev_err(&pdev->dev, "can't get car clk registers");
|
|
|
+ return PTR_ERR(tegra->clk_regs);
|
|
|
+ }
|
|
|
+ } else {
|
|
|
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
|
|
|
+ "ccroc-reg");
|
|
|
+ tegra->ccroc_regs = devm_ioremap_resource(&pdev->dev, res);
|
|
|
+ if (IS_ERR(tegra->ccroc_regs)) {
|
|
|
+ dev_err(&pdev->dev, "can't get ccroc registers");
|
|
|
+ return PTR_ERR(tegra->ccroc_regs);
|
|
|
+ }
|
|
|
+ }
|
|
|
|
|
|
tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
|
|
|
if (IS_ERR(tegra->reset)) {
|
|
|
@@ -580,6 +1382,8 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
|
|
|
if (err)
|
|
|
return err;
|
|
|
|
|
|
+ soctherm_init_hw_throt_cdev(pdev);
|
|
|
+
|
|
|
soctherm_init(pdev);
|
|
|
|
|
|
for (i = 0; i < soc->num_ttgs; ++i) {
|
|
|
@@ -593,6 +1397,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
|
|
|
zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
|
|
|
zone->dev = &pdev->dev;
|
|
|
zone->sg = soc->ttgs[i];
|
|
|
+ zone->ts = tegra;
|
|
|
|
|
|
z = devm_thermal_zone_of_sensor_register(&pdev->dev,
|
|
|
soc->ttgs[i]->id, zone,
|
|
|
@@ -608,7 +1413,9 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
|
|
|
tegra->thermctl_tzs[soc->ttgs[i]->id] = z;
|
|
|
|
|
|
/* Configure hw trip points */
|
|
|
- tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
|
|
|
+ err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
|
|
|
+ if (err)
|
|
|
+ goto disable_clocks;
|
|
|
}
|
|
|
|
|
|
soctherm_debug_init(pdev);
|
|
|
@@ -661,7 +1468,12 @@ static int __maybe_unused soctherm_resume(struct device *dev)
|
|
|
struct thermal_zone_device *tz;
|
|
|
|
|
|
tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
|
|
|
- tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
|
|
|
+ err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
|
|
|
+ if (err) {
|
|
|
+ dev_err(&pdev->dev,
|
|
|
+ "Resume failed: set hwtrips failed\n");
|
|
|
+ return err;
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
return 0;
|
Zhang Rui