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@@ -151,6 +151,8 @@ static int uvd_v6_0_hw_init(void *handle)
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uint32_t tmp;
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int r;
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+ amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
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+
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r = uvd_v6_0_start(adev);
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if (r)
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goto done;
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@@ -935,28 +937,12 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
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}
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#endif
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-static void uvd_v6_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
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-{
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- u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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-
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- if (enable)
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- tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
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- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
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- else
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- tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
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- GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
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-
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- WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
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-}
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-
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static int uvd_v6_0_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
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- uvd_v6_0_set_bypass_mode(adev, enable);
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-
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if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
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return 0;
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