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@@ -5627,6 +5627,17 @@ void intel_init_pm(struct drm_device *dev)
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}
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dev_priv->display.init_clock_gating = haswell_init_clock_gating;
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} else if (INTEL_INFO(dev)->gen == 8) {
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+ if (dev_priv->wm.pri_latency[0] &&
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+ dev_priv->wm.spr_latency[0] &&
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+ dev_priv->wm.cur_latency[0]) {
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+ dev_priv->display.update_wm = ilk_update_wm;
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+ dev_priv->display.update_sprite_wm =
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+ ilk_update_sprite_wm;
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+ } else {
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+ DRM_DEBUG_KMS("Failed to read display plane latency. "
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+ "Disable CxSR\n");
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+ dev_priv->display.update_wm = NULL;
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+ }
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dev_priv->display.init_clock_gating = gen8_init_clock_gating;
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} else
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dev_priv->display.update_wm = NULL;
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