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@@ -48,6 +48,9 @@ MODULE_PARM_DESC(ath10k_target_ps, "Enable ath10k Target (SoC) PS option");
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module_param_named(irq_mode, ath10k_pci_irq_mode, uint, 0644);
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MODULE_PARM_DESC(irq_mode, "0: auto, 1: legacy, 2: msi (default: 0)");
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+/* how long wait to wait for target to initialise, in ms */
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+#define ATH10K_PCI_TARGET_WAIT 3000
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+
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#define QCA988X_2_0_DEVICE_ID (0x003c)
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static DEFINE_PCI_DEVICE_TABLE(ath10k_pci_id_table) = {
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@@ -2385,30 +2388,41 @@ static int ath10k_pci_deinit_irq(struct ath10k *ar)
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static int ath10k_pci_wait_for_target_init(struct ath10k *ar)
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{
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struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
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- int wait_limit = 300; /* 3 sec */
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+ unsigned long timeout;
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int ret;
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+ u32 val;
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ret = ath10k_pci_wake(ar);
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if (ret) {
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- ath10k_err("failed to wake up target: %d\n", ret);
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+ ath10k_err("failed to wake up target for init: %d\n", ret);
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return ret;
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}
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- while (wait_limit-- &&
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- !(ioread32(ar_pci->mem + FW_INDICATOR_ADDRESS) &
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- FW_IND_INITIALIZED)) {
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+ timeout = jiffies + msecs_to_jiffies(ATH10K_PCI_TARGET_WAIT);
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+
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+ do {
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+ val = ath10k_pci_read32(ar, FW_INDICATOR_ADDRESS);
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+
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+ /* target should never return this */
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+ if (val == 0xffffffff)
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+ continue;
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+
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+ if (val & FW_IND_INITIALIZED)
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+ break;
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+
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if (ar_pci->num_msi_intrs == 0)
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/* Fix potential race by repeating CORE_BASE writes */
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- iowrite32(PCIE_INTR_FIRMWARE_MASK |
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- PCIE_INTR_CE_MASK_ALL,
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- ar_pci->mem + (SOC_CORE_BASE_ADDRESS |
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- PCIE_INTR_ENABLE_ADDRESS));
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+ ath10k_pci_soc_write32(ar, PCIE_INTR_ENABLE_ADDRESS,
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+ PCIE_INTR_FIRMWARE_MASK |
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+ PCIE_INTR_CE_MASK_ALL);
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+
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mdelay(10);
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- }
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+ } while (time_before(jiffies, timeout));
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- if (wait_limit < 0) {
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- ath10k_err("target stalled\n");
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- ret = -EIO;
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+ if (val == 0xffffffff || !(val & FW_IND_INITIALIZED)) {
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+ ath10k_err("failed to receive initialized event from target: %08x\n",
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+ val);
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+ ret = -ETIMEDOUT;
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goto out;
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}
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