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@@ -101,7 +101,7 @@ struct clk {
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#define CLK_PLL BIT(2) /* PLL-derived clock */
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#define PRE_PLL BIT(3) /* source is before PLL mult/div */
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#define FIXED_DIV_PLL BIT(4) /* fixed divisor from PLL */
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-#define FIXED_RATE_PLL BIT(5) /* fixed ouput rate PLL */
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+#define FIXED_RATE_PLL BIT(5) /* fixed output rate PLL */
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#define MAX_PLL_SYSCLKS 16
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