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@@ -284,16 +284,28 @@ static int sunxi_mmc_init_host(struct mmc_host *mmc)
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if (sunxi_mmc_reset_host(host))
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if (sunxi_mmc_reset_host(host))
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return -EIO;
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return -EIO;
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+ /*
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+ * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8
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+ *
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+ * TODO: sun9i has a larger FIFO and supports higher trigger values
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+ */
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mmc_writel(host, REG_FTRGL, 0x20070008);
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mmc_writel(host, REG_FTRGL, 0x20070008);
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+ /* Maximum timeout value */
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mmc_writel(host, REG_TMOUT, 0xffffffff);
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mmc_writel(host, REG_TMOUT, 0xffffffff);
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+ /* Unmask SDIO interrupt if needed */
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mmc_writel(host, REG_IMASK, host->sdio_imask);
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mmc_writel(host, REG_IMASK, host->sdio_imask);
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+ /* Clear all pending interrupts */
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mmc_writel(host, REG_RINTR, 0xffffffff);
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mmc_writel(host, REG_RINTR, 0xffffffff);
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+ /* Debug register? undocumented */
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mmc_writel(host, REG_DBGC, 0xdeb);
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mmc_writel(host, REG_DBGC, 0xdeb);
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+ /* Enable CEATA support */
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mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
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mmc_writel(host, REG_FUNS, SDXC_CEATA_ON);
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+ /* Set DMA descriptor list base address */
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mmc_writel(host, REG_DLBA, host->sg_dma);
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mmc_writel(host, REG_DLBA, host->sg_dma);
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rval = mmc_readl(host, REG_GCTRL);
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rval = mmc_readl(host, REG_GCTRL);
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rval |= SDXC_INTERRUPT_ENABLE_BIT;
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rval |= SDXC_INTERRUPT_ENABLE_BIT;
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+ /* Undocumented, but found in Allwinner code */
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rval &= ~SDXC_ACCESS_DONE_DIRECT;
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rval &= ~SDXC_ACCESS_DONE_DIRECT;
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mmc_writel(host, REG_GCTRL, rval);
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mmc_writel(host, REG_GCTRL, rval);
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