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@@ -309,6 +309,7 @@
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/* HFSCR and FSCR bit numbers are the same */
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/* HFSCR and FSCR bit numbers are the same */
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#define FSCR_LM_LG 11 /* Enable Load Monitor Registers */
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#define FSCR_LM_LG 11 /* Enable Load Monitor Registers */
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+#define FSCR_MSGP_LG 10 /* Enable MSGP */
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#define FSCR_TAR_LG 8 /* Enable Target Address Register */
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#define FSCR_TAR_LG 8 /* Enable Target Address Register */
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#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
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#define FSCR_EBB_LG 7 /* Enable Event Based Branching */
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#define FSCR_TM_LG 5 /* Enable Transactional Memory */
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#define FSCR_TM_LG 5 /* Enable Transactional Memory */
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@@ -324,6 +325,7 @@
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#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
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#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
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#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
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#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
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#define HFSCR_LM __MASK(FSCR_LM_LG)
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#define HFSCR_LM __MASK(FSCR_LM_LG)
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+#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
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#define HFSCR_TAR __MASK(FSCR_TAR_LG)
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#define HFSCR_TAR __MASK(FSCR_TAR_LG)
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#define HFSCR_EBB __MASK(FSCR_EBB_LG)
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#define HFSCR_EBB __MASK(FSCR_EBB_LG)
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#define HFSCR_TM __MASK(FSCR_TM_LG)
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#define HFSCR_TM __MASK(FSCR_TM_LG)
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