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+/*
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+ * Copyright © 2014 Intel Corporation
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice (including the next
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+ * paragraph) shall be included in all copies or substantial portions of the
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+ * Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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+ * IN THE SOFTWARE.
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+ *
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+ * Please try to maintain the following order within this file unless it makes
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+ * sense to do otherwise. From top to bottom:
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+ * 1. typedefs
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+ * 2. #defines, and macros
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+ * 3. structure definitions
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+ * 4. function prototypes
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+ *
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+ * Within each section, please try to order by generation in ascending order,
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+ * from top to bottom (ie. gen6 on the top, gen8 on the bottom).
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+ */
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+
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+#ifndef __I915_GEM_GTT_H__
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+#define __I915_GEM_GTT_H__
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+
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+typedef uint32_t gen6_gtt_pte_t;
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+typedef uint64_t gen8_gtt_pte_t;
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+typedef gen8_gtt_pte_t gen8_ppgtt_pde_t;
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+
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+#define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
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+
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+#define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t))
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+/* gen6-hsw has bit 11-4 for physical addr bit 39-32 */
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+#define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0))
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+#define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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+#define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr)
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+#define GEN6_PTE_CACHE_LLC (2 << 1)
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+#define GEN6_PTE_UNCACHED (1 << 1)
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+#define GEN6_PTE_VALID (1 << 0)
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+
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+#define GEN6_PPGTT_PD_ENTRIES 512
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+#define GEN6_PD_SIZE (GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE)
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+#define GEN6_PD_ALIGN (PAGE_SIZE * 16)
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+#define GEN6_PDE_VALID (1 << 0)
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+
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+#define GEN7_PTE_CACHE_L3_LLC (3 << 1)
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+
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+#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
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+#define BYT_PTE_WRITEABLE (1 << 1)
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+
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+/* Cacheability Control is a 4-bit value. The low three bits are stored in bits
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+ * 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
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+ */
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+#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \
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+ (((bits) & 0x8) << (11 - 3)))
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+#define HSW_WB_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x2)
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+#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3)
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+#define HSW_WB_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x8)
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+#define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb)
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+#define HSW_WT_ELLC_LLC_AGE3 HSW_CACHEABILITY_CONTROL(0x7)
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+#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
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+#define HSW_PTE_UNCACHED (0)
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+#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0))
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+#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr)
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+
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+/* GEN8 legacy style address is defined as a 3 level page table:
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+ * 31:30 | 29:21 | 20:12 | 11:0
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+ * PDPE | PDE | PTE | offset
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+ * The difference as compared to normal x86 3 level page table is the PDPEs are
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+ * programmed via register.
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+ */
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+#define GEN8_PDPE_SHIFT 30
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+#define GEN8_PDPE_MASK 0x3
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+#define GEN8_PDE_SHIFT 21
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+#define GEN8_PDE_MASK 0x1ff
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+#define GEN8_PTE_SHIFT 12
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+#define GEN8_PTE_MASK 0x1ff
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+#define GEN8_LEGACY_PDPS 4
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+#define GEN8_PTES_PER_PAGE (PAGE_SIZE / sizeof(gen8_gtt_pte_t))
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+#define GEN8_PDES_PER_PAGE (PAGE_SIZE / sizeof(gen8_ppgtt_pde_t))
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+
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+#define PPAT_UNCACHED_INDEX (_PAGE_PWT | _PAGE_PCD)
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+#define PPAT_CACHED_PDE_INDEX 0 /* WB LLC */
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+#define PPAT_CACHED_INDEX _PAGE_PAT /* WB LLCeLLC */
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+#define PPAT_DISPLAY_ELLC_INDEX _PAGE_PCD /* WT eLLC */
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+
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+#define GEN8_PPAT_AGE(x) (x<<4)
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+#define GEN8_PPAT_LLCeLLC (3<<2)
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+#define GEN8_PPAT_LLCELLC (2<<2)
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+#define GEN8_PPAT_LLC (1<<2)
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+#define GEN8_PPAT_WB (3<<0)
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+#define GEN8_PPAT_WT (2<<0)
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+#define GEN8_PPAT_WC (1<<0)
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+#define GEN8_PPAT_UC (0<<0)
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+#define GEN8_PPAT_ELLC_OVERRIDE (0<<2)
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+#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
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+
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+enum i915_cache_level;
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+/**
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+ * A VMA represents a GEM BO that is bound into an address space. Therefore, a
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+ * VMA's presence cannot be guaranteed before binding, or after unbinding the
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+ * object into/from the address space.
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+ *
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+ * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
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+ * will always be <= an objects lifetime. So object refcounting should cover us.
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+ */
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+struct i915_vma {
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+ struct drm_mm_node node;
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+ struct drm_i915_gem_object *obj;
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+ struct i915_address_space *vm;
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+
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+ /** This object's place on the active/inactive lists */
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+ struct list_head mm_list;
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+
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+ struct list_head vma_link; /* Link in the object's VMA list */
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+
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+ /** This vma's place in the batchbuffer or on the eviction list */
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+ struct list_head exec_list;
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+
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+ /**
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+ * Used for performing relocations during execbuffer insertion.
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+ */
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+ struct hlist_node exec_node;
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+ unsigned long exec_handle;
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+ struct drm_i915_gem_exec_object2 *exec_entry;
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+
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+ /**
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+ * How many users have pinned this object in GTT space. The following
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+ * users can each hold at most one reference: pwrite/pread, pin_ioctl
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+ * (via user_pin_count), execbuffer (objects are not allowed multiple
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+ * times for the same batchbuffer), and the framebuffer code. When
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+ * switching/pageflipping, the framebuffer code has at most two buffers
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+ * pinned per crtc.
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+ *
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+ * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
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+ * bits with absolutely no headroom. So use 4 bits. */
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+ unsigned int pin_count:4;
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+#define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
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+
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+ /** Unmap an object from an address space. This usually consists of
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+ * setting the valid PTE entries to a reserved scratch page. */
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+ void (*unbind_vma)(struct i915_vma *vma);
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+ /* Map an object into an address space with the given cache flags. */
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+#define GLOBAL_BIND (1<<0)
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+ void (*bind_vma)(struct i915_vma *vma,
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+ enum i915_cache_level cache_level,
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+ u32 flags);
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+};
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+
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+struct i915_address_space {
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+ struct drm_mm mm;
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+ struct drm_device *dev;
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+ struct list_head global_link;
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+ unsigned long start; /* Start offset always 0 for dri2 */
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+ size_t total; /* size addr space maps (ex. 2GB for ggtt) */
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+
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+ struct {
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+ dma_addr_t addr;
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+ struct page *page;
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+ } scratch;
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+
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+ /**
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+ * List of objects currently involved in rendering.
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+ *
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+ * Includes buffers having the contents of their GPU caches
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+ * flushed, not necessarily primitives. last_rendering_seqno
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+ * represents when the rendering involved will be completed.
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+ *
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+ * A reference is held on the buffer while on this list.
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+ */
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+ struct list_head active_list;
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+
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+ /**
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+ * LRU list of objects which are not in the ringbuffer and
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+ * are ready to unbind, but are still in the GTT.
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+ *
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+ * last_rendering_seqno is 0 while an object is in this list.
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+ *
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+ * A reference is not held on the buffer while on this list,
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+ * as merely being GTT-bound shouldn't prevent its being
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+ * freed, and we'll pull it off the list in the free path.
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+ */
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+ struct list_head inactive_list;
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+
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+ /* FIXME: Need a more generic return type */
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+ gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
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+ enum i915_cache_level level,
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+ bool valid); /* Create a valid PTE */
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+ void (*clear_range)(struct i915_address_space *vm,
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+ uint64_t start,
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+ uint64_t length,
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+ bool use_scratch);
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+ void (*insert_entries)(struct i915_address_space *vm,
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+ struct sg_table *st,
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+ uint64_t start,
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+ enum i915_cache_level cache_level);
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+ void (*cleanup)(struct i915_address_space *vm);
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+};
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+
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+/* The Graphics Translation Table is the way in which GEN hardware translates a
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+ * Graphics Virtual Address into a Physical Address. In addition to the normal
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+ * collateral associated with any va->pa translations GEN hardware also has a
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+ * portion of the GTT which can be mapped by the CPU and remain both coherent
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+ * and correct (in cases like swizzling). That region is referred to as GMADR in
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+ * the spec.
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+ */
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+struct i915_gtt {
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+ struct i915_address_space base;
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+ size_t stolen_size; /* Total size of stolen memory */
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+
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+ unsigned long mappable_end; /* End offset that we can CPU map */
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+ struct io_mapping *mappable; /* Mapping to our CPU mappable region */
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+ phys_addr_t mappable_base; /* PA of our GMADR */
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+
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+ /** "Graphics Stolen Memory" holds the global PTEs */
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+ void __iomem *gsm;
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+
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+ bool do_idle_maps;
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+
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+ int mtrr;
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+
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+ /* global gtt ops */
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+ int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
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+ size_t *stolen, phys_addr_t *mappable_base,
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+ unsigned long *mappable_end);
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+};
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+
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+struct i915_hw_ppgtt {
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+ struct i915_address_space base;
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+ struct kref ref;
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+ struct drm_mm_node node;
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+ unsigned num_pd_entries;
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+ unsigned num_pd_pages; /* gen8+ */
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+ union {
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+ struct page **pt_pages;
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+ struct page **gen8_pt_pages[GEN8_LEGACY_PDPS];
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+ };
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+ struct page *pd_pages;
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+ union {
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+ uint32_t pd_offset;
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+ dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS];
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+ };
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+ union {
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+ dma_addr_t *pt_dma_addr;
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+ dma_addr_t *gen8_pt_dma_addr[4];
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+ };
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+
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+ struct i915_hw_context *ctx;
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+
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+ int (*enable)(struct i915_hw_ppgtt *ppgtt);
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+ int (*switch_mm)(struct i915_hw_ppgtt *ppgtt,
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+ struct intel_ring_buffer *ring,
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+ bool synchronous);
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+ void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m);
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+};
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+
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+int i915_gem_gtt_init(struct drm_device *dev);
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+void i915_gem_init_global_gtt(struct drm_device *dev);
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+void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
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+ unsigned long mappable_end, unsigned long end);
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+
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+bool intel_enable_ppgtt(struct drm_device *dev, bool full);
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+int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt);
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+
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+void i915_check_and_clear_faults(struct drm_device *dev);
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+void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
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+void i915_gem_restore_gtt_mappings(struct drm_device *dev);
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+
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+int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
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+void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
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+
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+#endif
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Ben Widawsky