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@@ -1,52 +1,33 @@
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-DesignWare HDMI bridge bindings
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-
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-Required properties:
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-- compatible: platform specific such as:
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- * "snps,dw-hdmi-tx"
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- * "fsl,imx6q-hdmi"
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- * "fsl,imx6dl-hdmi"
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- * "rockchip,rk3288-dw-hdmi"
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-- reg: Physical base address and length of the controller's registers.
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-- interrupts: The HDMI interrupt number
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-- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
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- as described in Documentation/devicetree/bindings/clock/clock-bindings.txt,
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- the clocks are soc specific, the clock-names should be "iahb", "isfr"
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--port@[X]: SoC specific port nodes with endpoint definitions as defined
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- in Documentation/devicetree/bindings/media/video-interfaces.txt,
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- please refer to the SoC specific binding document:
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- * Documentation/devicetree/bindings/display/imx/hdmi.txt
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- * Documentation/devicetree/bindings/display/rockchip/dw_hdmi-rockchip.txt
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-
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-Optional properties
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-- reg-io-width: the width of the reg:1,4, default set to 1 if not present
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-- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing,
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- if the property is omitted, a functionally reduced I2C bus
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- controller on DW HDMI is probed
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-- clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec"
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-
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-Example:
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- hdmi: hdmi@0120000 {
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- compatible = "fsl,imx6q-hdmi";
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- reg = <0x00120000 0x9000>;
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- interrupts = <0 115 0x04>;
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- gpr = <&gpr>;
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- clocks = <&clks 123>, <&clks 124>;
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- clock-names = "iahb", "isfr";
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- ddc-i2c-bus = <&i2c2>;
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-
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- port@0 {
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- reg = <0>;
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-
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- hdmi_mux_0: endpoint {
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- remote-endpoint = <&ipu1_di0_hdmi>;
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- };
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- };
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-
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- port@1 {
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- reg = <1>;
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-
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- hdmi_mux_1: endpoint {
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- remote-endpoint = <&ipu1_di1_hdmi>;
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- };
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- };
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- };
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+Synopsys DesignWare HDMI TX Encoder
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+===================================
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+
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+This document defines device tree properties for the Synopsys DesignWare HDMI
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+TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
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+specification by itself but is meant to be referenced by platform-specific
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+device tree bindings.
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+
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+When referenced from platform device tree bindings the properties defined in
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+this document are defined as follows. The platform device tree bindings are
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+responsible for defining whether each property is required or optional.
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+
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+- reg: Memory mapped base address and length of the DWC HDMI TX registers.
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+
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+- reg-io-width: Width of the registers specified by the reg property. The
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+ value is expressed in bytes and must be equal to 1 or 4 if specified. The
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+ register width defaults to 1 if the property is not present.
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+
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+- interrupts: Reference to the DWC HDMI TX interrupt.
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+
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+- clocks: References to all the clocks specified in the clock-names property
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+ as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
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+
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+- clock-names: The DWC HDMI TX uses the following clocks.
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+
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+ - "iahb" is the bus clock for either AHB and APB (mandatory).
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+ - "isfr" is the internal register configuration clock (mandatory).
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+ - "cec" is the HDMI CEC controller main clock (optional).
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+
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+- ports: The connectivity of the DWC HDMI TX with the rest of the system is
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+ expressed in using ports as specified in the device graph bindings defined
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+ in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
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+ is platform-specific.
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Laurent Pinchart