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@@ -11,6 +11,7 @@
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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+#include <linux/bootmem.h>
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#include <linux/bug.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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@@ -56,7 +57,7 @@
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#define F_MMU_TF_PROTECT_SEL(prot) (((prot) & 0x3) << 5)
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#define REG_MMU_IVRP_PADDR 0x114
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-#define F_MMU_IVRP_PA_SET(pa) ((pa) >> 1)
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+#define F_MMU_IVRP_PA_SET(pa, ext) (((pa) >> 1) | ((!!(ext)) << 31))
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#define REG_MMU_INT_CONTROL0 0x120
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#define F_L2_MULIT_HIT_EN BIT(0)
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@@ -125,6 +126,7 @@ struct mtk_iommu_data {
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struct mtk_iommu_domain *m4u_dom;
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struct iommu_group *m4u_group;
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struct mtk_smi_iommu smi_imu; /* SMI larb iommu info */
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+ bool enable_4GB;
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};
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static struct iommu_ops mtk_iommu_ops;
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@@ -257,6 +259,9 @@ static int mtk_iommu_domain_finalise(struct mtk_iommu_data *data)
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.iommu_dev = data->dev,
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};
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+ if (data->enable_4GB)
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+ dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_4GB;
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+
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dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data);
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if (!dom->iop) {
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dev_err(data->dev, "Failed to alloc io pgtable\n");
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@@ -530,7 +535,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
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F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
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writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
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- writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base),
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+ writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
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data->base + REG_MMU_IVRP_PADDR);
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writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
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@@ -591,6 +596,9 @@ static int mtk_iommu_probe(struct platform_device *pdev)
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return -ENOMEM;
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data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN);
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+ /* Whether the current dram is over 4GB */
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+ data->enable_4GB = !!(max_pfn > (0xffffffffUL >> PAGE_SHIFT));
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+
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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data->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(data->base))
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@@ -690,7 +698,7 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
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writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG);
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writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0);
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writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL);
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- writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base),
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+ writel_relaxed(F_MMU_IVRP_PA_SET(data->protect_base, data->enable_4GB),
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base + REG_MMU_IVRP_PADDR);
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return 0;
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}
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