drm/nouveau/bus: cosmetic changes

This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/subdev/bus.h

@@ -8,7 +8,7 @@ struct nvkm_bus_intr {
 };
 
 struct nvkm_bus {
-	struct nvkm_subdev base;
+	struct nvkm_subdev subdev;
 	int (*hwsq_exec)(struct nvkm_bus *, u32 *, u32);
 	u32 hwsq_size;
 };
@@ -23,11 +23,11 @@ nvkm_bus(void *obj)
 	nvkm_subdev_create_((p), (e), (o), 0, "PBUS", "master",             \
 			       sizeof(**d), (void **)d)
 #define nvkm_bus_destroy(p)                                                 \
-	nvkm_subdev_destroy(&(p)->base)
+	nvkm_subdev_destroy(&(p)->subdev)
 #define nvkm_bus_init(p)                                                    \
-	nvkm_subdev_init(&(p)->base)
+	nvkm_subdev_init(&(p)->subdev)
 #define nvkm_bus_fini(p, s)                                                 \
-	nvkm_subdev_fini(&(p)->base, (s))
+	nvkm_subdev_fini(&(p)->subdev, (s))
 
 #define _nvkm_bus_dtor _nvkm_subdev_dtor
 #define _nvkm_bus_init _nvkm_subdev_init

drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.c

@@ -27,20 +27,19 @@
 #include <subdev/timer.h>
 
 static int
-g94_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
+g94_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
 {
-	struct nv50_bus_priv *priv = (void *)pbus;
 	int i;
 
-	nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
-	nv_wr32(pbus, 0x001304, 0x00000000);
-	nv_wr32(pbus, 0x001318, 0x00000000);
+	nv_mask(bus, 0x001098, 0x00000008, 0x00000000);
+	nv_wr32(bus, 0x001304, 0x00000000);
+	nv_wr32(bus, 0x001318, 0x00000000);
 	for (i = 0; i < size; i++)
-		nv_wr32(priv, 0x080000 + (i * 4), data[i]);
-	nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
-	nv_wr32(pbus, 0x00130c, 0x00000001);
+		nv_wr32(bus, 0x080000 + (i * 4), data[i]);
+	nv_mask(bus, 0x001098, 0x00000018, 0x00000018);
+	nv_wr32(bus, 0x00130c, 0x00000001);
 
-	return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
+	return nv_wait(bus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
 }
 
 struct nvkm_oclass *

drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.c

@@ -27,43 +27,43 @@
 static void
 gf100_bus_intr(struct nvkm_subdev *subdev)
 {
-	struct nvkm_bus *pbus = nvkm_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
+	struct nvkm_bus *bus = nvkm_bus(subdev);
+	u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140);
 
 	if (stat & 0x0000000e) {
-		u32 addr = nv_rd32(pbus, 0x009084);
-		u32 data = nv_rd32(pbus, 0x009088);
+		u32 addr = nv_rd32(bus, 0x009084);
+		u32 data = nv_rd32(bus, 0x009088);
 
-		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
+		nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x [ %s%s%s]\n",
 			 (addr & 0x00000002) ? "write" : "read", data,
 			 (addr & 0x00fffffc),
 			 (stat & 0x00000002) ? "!ENGINE " : "",
 			 (stat & 0x00000004) ? "IBUS " : "",
 			 (stat & 0x00000008) ? "TIMEOUT " : "");
 
-		nv_wr32(pbus, 0x009084, 0x00000000);
-		nv_wr32(pbus, 0x001100, (stat & 0x0000000e));
+		nv_wr32(bus, 0x009084, 0x00000000);
+		nv_wr32(bus, 0x001100, (stat & 0x0000000e));
 		stat &= ~0x0000000e;
 	}
 
 	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0x00000000);
+		nv_error(bus, "unknown intr 0x%08x\n", stat);
+		nv_mask(bus, 0x001140, stat, 0x00000000);
 	}
 }
 
 static int
 gf100_bus_init(struct nvkm_object *object)
 {
-	struct nv04_bus_priv *priv = (void *)object;
+	struct nvkm_bus *bus = (void *)object;
 	int ret;
 
-	ret = nvkm_bus_init(&priv->base);
+	ret = nvkm_bus_init(bus);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x0000000e);
+	nv_wr32(bus, 0x001100, 0xffffffff);
+	nv_wr32(bus, 0x001140, 0x0000000e);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.c

@@ -24,7 +24,7 @@
 #include <subdev/bus.h>
 
 struct nvkm_hwsq {
-	struct nvkm_bus *pbus;
+	struct nvkm_bus *bus;
 	u32 addr;
 	u32 data;
 	struct {
@@ -41,13 +41,13 @@ hwsq_cmd(struct nvkm_hwsq *hwsq, int size, u8 data[])
 }
 
 int
-nvkm_hwsq_init(struct nvkm_bus *pbus, struct nvkm_hwsq **phwsq)
+nvkm_hwsq_init(struct nvkm_bus *bus, struct nvkm_hwsq **phwsq)
 {
 	struct nvkm_hwsq *hwsq;
 
 	hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
 	if (hwsq) {
-		hwsq->pbus = pbus;
+		hwsq->bus = bus;
 		hwsq->addr = ~0;
 		hwsq->data = ~0;
 		memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
@@ -63,21 +63,21 @@ nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
 	struct nvkm_hwsq *hwsq = *phwsq;
 	int ret = 0, i;
 	if (hwsq) {
-		struct nvkm_bus *pbus = hwsq->pbus;
+		struct nvkm_bus *bus = hwsq->bus;
 		hwsq->c.size = (hwsq->c.size + 4) / 4;
-		if (hwsq->c.size <= pbus->hwsq_size) {
+		if (hwsq->c.size <= bus->hwsq_size) {
 			if (exec)
-				ret = pbus->hwsq_exec(pbus, (u32 *)hwsq->c.data,
+				ret = bus->hwsq_exec(bus, (u32 *)hwsq->c.data,
 						      hwsq->c.size);
 			if (ret)
-				nv_error(pbus, "hwsq exec failed: %d\n", ret);
+				nv_error(bus, "hwsq exec failed: %d\n", ret);
 		} else {
-			nv_error(pbus, "hwsq ucode too large\n");
+			nv_error(bus, "hwsq ucode too large\n");
 			ret = -ENOSPC;
 		}
 
 		for (i = 0; ret && i < hwsq->c.size; i++)
-			nv_error(pbus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);
+			nv_error(bus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);
 
 		*phwsq = NULL;
 		kfree(hwsq);
@@ -88,7 +88,7 @@ nvkm_hwsq_fini(struct nvkm_hwsq **phwsq, bool exec)
 void
 nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
 {
-	nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);
+	nv_debug(hwsq->bus, "R[%06x] = 0x%08x\n", addr, data);
 
 	if (hwsq->data != data) {
 		if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
@@ -113,7 +113,7 @@ nvkm_hwsq_wr32(struct nvkm_hwsq *hwsq, u32 addr, u32 data)
 void
 nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
 {
-	nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
+	nv_debug(hwsq->bus, " FLAG[%02x] = %d\n", flag, data);
 	flag += 0x80;
 	if (data >= 0)
 		flag += 0x20;
@@ -125,7 +125,7 @@ nvkm_hwsq_setf(struct nvkm_hwsq *hwsq, u8 flag, int data)
 void
 nvkm_hwsq_wait(struct nvkm_hwsq *hwsq, u8 flag, u8 data)
 {
-	nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
+	nv_debug(hwsq->bus, " WAIT[%02x] = %d\n", flag, data);
 	hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
 }
 
@@ -138,6 +138,6 @@ nvkm_hwsq_nsec(struct nvkm_hwsq *hwsq, u32 nsec)
 		shift++;
 	}
 
-	nv_debug(hwsq->pbus, "    DELAY = %d ns\n", nsec);
+	nv_debug(hwsq->bus, "    DELAY = %d ns\n", nsec);
 	hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
 }

drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.h

@@ -59,10 +59,10 @@ hwsq_reg(u32 addr)
 static inline int
 hwsq_init(struct hwsq *ram, struct nvkm_subdev *subdev)
 {
-	struct nvkm_bus *pbus = nvkm_bus(subdev);
+	struct nvkm_bus *bus = nvkm_bus(subdev);
 	int ret;
 
-	ret = nvkm_hwsq_init(pbus, &ram->hwsq);
+	ret = nvkm_hwsq_init(bus, &ram->hwsq);
 	if (ret)
 		return ret;
 

drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.c

@@ -27,13 +27,13 @@
 static void
 nv04_bus_intr(struct nvkm_subdev *subdev)
 {
-	struct nvkm_bus *pbus = nvkm_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
+	struct nvkm_bus *bus = nvkm_bus(subdev);
+	u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140);
 
 	if (stat & 0x00000001) {
-		nv_error(pbus, "BUS ERROR\n");
+		nv_error(bus, "BUS ERROR\n");
 		stat &= ~0x00000001;
-		nv_wr32(pbus, 0x001100, 0x00000001);
+		nv_wr32(bus, 0x001100, 0x00000001);
 	}
 
 	if (stat & 0x00000110) {
@@ -41,24 +41,24 @@ nv04_bus_intr(struct nvkm_subdev *subdev)
 		if (subdev && subdev->intr)
 			subdev->intr(subdev);
 		stat &= ~0x00000110;
-		nv_wr32(pbus, 0x001100, 0x00000110);
+		nv_wr32(bus, 0x001100, 0x00000110);
 	}
 
 	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0x00000000);
+		nv_error(bus, "unknown intr 0x%08x\n", stat);
+		nv_mask(bus, 0x001140, stat, 0x00000000);
 	}
 }
 
 static int
 nv04_bus_init(struct nvkm_object *object)
 {
-	struct nv04_bus_priv *priv = (void *)object;
+	struct nvkm_bus *bus = (void *)object;
 
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x00000111);
+	nv_wr32(bus, 0x001100, 0xffffffff);
+	nv_wr32(bus, 0x001140, 0x00000111);
 
-	return nvkm_bus_init(&priv->base);
+	return nvkm_bus_init(bus);
 }
 
 int
@@ -67,17 +67,17 @@ nv04_bus_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	      struct nvkm_object **pobject)
 {
 	struct nv04_bus_impl *impl = (void *)oclass;
-	struct nv04_bus_priv *priv;
+	struct nvkm_bus *bus;
 	int ret;
 
-	ret = nvkm_bus_create(parent, engine, oclass, &priv);
-	*pobject = nv_object(priv);
+	ret = nvkm_bus_create(parent, engine, oclass, &bus);
+	*pobject = nv_object(bus);
 	if (ret)
 		return ret;
 
-	nv_subdev(priv)->intr = impl->intr;
-	priv->base.hwsq_exec = impl->hwsq_exec;
-	priv->base.hwsq_size = impl->hwsq_size;
+	nv_subdev(bus)->intr = impl->intr;
+	bus->hwsq_exec = impl->hwsq_exec;
+	bus->hwsq_size = impl->hwsq_size;
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.h

@@ -2,10 +2,6 @@
 #define __NVKM_BUS_NV04_H__
 #include <subdev/bus.h>
 
-struct nv04_bus_priv {
-	struct nvkm_bus base;
-};
-
 int  nv04_bus_ctor(struct nvkm_object *, struct nvkm_object *,
 		   struct nvkm_oclass *, void *, u32,
 		   struct nvkm_object **);

drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.c

@@ -27,54 +27,54 @@
 static void
 nv31_bus_intr(struct nvkm_subdev *subdev)
 {
-	struct nvkm_bus *pbus = nvkm_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
-	u32 gpio = nv_rd32(pbus, 0x001104) & nv_rd32(pbus, 0x001144);
+	struct nvkm_bus *bus = nvkm_bus(subdev);
+	u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140);
+	u32 gpio = nv_rd32(bus, 0x001104) & nv_rd32(bus, 0x001144);
 
 	if (gpio) {
-		subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_GPIO);
+		subdev = nvkm_subdev(bus, NVDEV_SUBDEV_GPIO);
 		if (subdev && subdev->intr)
 			subdev->intr(subdev);
 	}
 
 	if (stat & 0x00000008) {  /* NV41- */
-		u32 addr = nv_rd32(pbus, 0x009084);
-		u32 data = nv_rd32(pbus, 0x009088);
+		u32 addr = nv_rd32(bus, 0x009084);
+		u32 data = nv_rd32(bus, 0x009088);
 
-		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
+		nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
 			 (addr & 0x00000002) ? "write" : "read", data,
 			 (addr & 0x00fffffc));
 
 		stat &= ~0x00000008;
-		nv_wr32(pbus, 0x001100, 0x00000008);
+		nv_wr32(bus, 0x001100, 0x00000008);
 	}
 
 	if (stat & 0x00070000) {
-		subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
+		subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM);
 		if (subdev && subdev->intr)
 			subdev->intr(subdev);
 		stat &= ~0x00070000;
-		nv_wr32(pbus, 0x001100, 0x00070000);
+		nv_wr32(bus, 0x001100, 0x00070000);
 	}
 
 	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0x00000000);
+		nv_error(bus, "unknown intr 0x%08x\n", stat);
+		nv_mask(bus, 0x001140, stat, 0x00000000);
 	}
 }
 
 static int
 nv31_bus_init(struct nvkm_object *object)
 {
-	struct nv04_bus_priv *priv = (void *)object;
+	struct nvkm_bus *bus = (void *)object;
 	int ret;
 
-	ret = nvkm_bus_init(&priv->base);
+	ret = nvkm_bus_init(bus);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x00070008);
+	nv_wr32(bus, 0x001100, 0xffffffff);
+	nv_wr32(bus, 0x001140, 0x00070008);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.c

@@ -27,65 +27,64 @@
 #include <subdev/timer.h>
 
 static int
-nv50_bus_hwsq_exec(struct nvkm_bus *pbus, u32 *data, u32 size)
+nv50_bus_hwsq_exec(struct nvkm_bus *bus, u32 *data, u32 size)
 {
-	struct nv50_bus_priv *priv = (void *)pbus;
 	int i;
 
-	nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
-	nv_wr32(pbus, 0x001304, 0x00000000);
+	nv_mask(bus, 0x001098, 0x00000008, 0x00000000);
+	nv_wr32(bus, 0x001304, 0x00000000);
 	for (i = 0; i < size; i++)
-		nv_wr32(priv, 0x001400 + (i * 4), data[i]);
-	nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
-	nv_wr32(pbus, 0x00130c, 0x00000003);
+		nv_wr32(bus, 0x001400 + (i * 4), data[i]);
+	nv_mask(bus, 0x001098, 0x00000018, 0x00000018);
+	nv_wr32(bus, 0x00130c, 0x00000003);
 
-	return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
+	return nv_wait(bus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
 }
 
 void
 nv50_bus_intr(struct nvkm_subdev *subdev)
 {
-	struct nvkm_bus *pbus = nvkm_bus(subdev);
-	u32 stat = nv_rd32(pbus, 0x001100) & nv_rd32(pbus, 0x001140);
+	struct nvkm_bus *bus = nvkm_bus(subdev);
+	u32 stat = nv_rd32(bus, 0x001100) & nv_rd32(bus, 0x001140);
 
 	if (stat & 0x00000008) {
-		u32 addr = nv_rd32(pbus, 0x009084);
-		u32 data = nv_rd32(pbus, 0x009088);
+		u32 addr = nv_rd32(bus, 0x009084);
+		u32 data = nv_rd32(bus, 0x009088);
 
-		nv_error(pbus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
+		nv_error(bus, "MMIO %s of 0x%08x FAULT at 0x%06x\n",
 			 (addr & 0x00000002) ? "write" : "read", data,
 			 (addr & 0x00fffffc));
 
 		stat &= ~0x00000008;
-		nv_wr32(pbus, 0x001100, 0x00000008);
+		nv_wr32(bus, 0x001100, 0x00000008);
 	}
 
 	if (stat & 0x00010000) {
-		subdev = nvkm_subdev(pbus, NVDEV_SUBDEV_THERM);
+		subdev = nvkm_subdev(bus, NVDEV_SUBDEV_THERM);
 		if (subdev && subdev->intr)
 			subdev->intr(subdev);
 		stat &= ~0x00010000;
-		nv_wr32(pbus, 0x001100, 0x00010000);
+		nv_wr32(bus, 0x001100, 0x00010000);
 	}
 
 	if (stat) {
-		nv_error(pbus, "unknown intr 0x%08x\n", stat);
-		nv_mask(pbus, 0x001140, stat, 0);
+		nv_error(bus, "unknown intr 0x%08x\n", stat);
+		nv_mask(bus, 0x001140, stat, 0);
 	}
 }
 
 int
 nv50_bus_init(struct nvkm_object *object)
 {
-	struct nv04_bus_priv *priv = (void *)object;
+	struct nvkm_bus *bus = (void *)object;
 	int ret;
 
-	ret = nvkm_bus_init(&priv->base);
+	ret = nvkm_bus_init(bus);
 	if (ret)
 		return ret;
 
-	nv_wr32(priv, 0x001100, 0xffffffff);
-	nv_wr32(priv, 0x001140, 0x00010008);
+	nv_wr32(bus, 0x001100, 0xffffffff);
+	nv_wr32(bus, 0x001140, 0x00010008);
 	return 0;
 }