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@@ -5815,6 +5815,7 @@ enum punit_power_well {
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#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
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#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
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#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
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+#define TRANS_DDI_DP_VC_PAYLOAD_ALLOC (1<<8)
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#define TRANS_DDI_BFI_ENABLE (1<<4)
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/* DisplayPort Transport Control */
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@@ -5824,6 +5825,7 @@ enum punit_power_well {
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#define DP_TP_CTL_ENABLE (1<<31)
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#define DP_TP_CTL_MODE_SST (0<<27)
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#define DP_TP_CTL_MODE_MST (1<<27)
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+#define DP_TP_CTL_FORCE_ACT (1<<25)
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#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
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#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
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#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
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@@ -5838,8 +5840,13 @@ enum punit_power_well {
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#define DP_TP_STATUS_A 0x64044
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#define DP_TP_STATUS_B 0x64144
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#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
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-#define DP_TP_STATUS_IDLE_DONE (1<<25)
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-#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
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+#define DP_TP_STATUS_IDLE_DONE (1<<25)
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+#define DP_TP_STATUS_ACT_SENT (1<<24)
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+#define DP_TP_STATUS_MODE_STATUS_MST (1<<23)
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+#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
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+#define DP_TP_STATUS_PAYLOAD_MAPPING_VC2 (3 << 8)
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+#define DP_TP_STATUS_PAYLOAD_MAPPING_VC1 (3 << 4)
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+#define DP_TP_STATUS_PAYLOAD_MAPPING_VC0 (3 << 0)
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/* DDI Buffer Control */
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#define DDI_BUF_CTL_A 0x64000
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