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@@ -696,7 +696,7 @@ static int vce_v3_0_process_interrupt(struct amdgpu_device *adev,
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return 0;
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return 0;
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}
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}
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-static void vce_v3_set_bypass_mode(struct amdgpu_device *adev, bool enable)
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+static void vce_v3_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
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{
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{
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u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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@@ -716,7 +716,7 @@ static int vce_v3_0_set_clockgating_state(void *handle,
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int i;
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int i;
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if (adev->asic_type == CHIP_POLARIS10)
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if (adev->asic_type == CHIP_POLARIS10)
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- vce_v3_set_bypass_mode(adev, enable);
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+ vce_v3_0_set_bypass_mode(adev, enable);
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if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
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if (!(adev->cg_flags & AMD_CG_SUPPORT_VCE_MGCG))
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return 0;
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return 0;
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