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@@ -124,7 +124,9 @@
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#define VNDMR2_VPS (1 << 30)
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#define VNDMR2_HPS (1 << 29)
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#define VNDMR2_FTEV (1 << 17)
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+#define VNDMR2_FTEH (1 << 16)
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#define VNDMR2_VLV(n) ((n & 0xf) << 12)
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+#define VNDMR2_HLV(n) ((n) & 0xfff)
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/* Video n CSI2 Interface Mode Register (Gen3) */
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#define VNCSI_IFMD_DES1 (1 << 26)
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@@ -612,8 +614,9 @@ void rvin_crop_scale_comp(struct rvin_dev *vin)
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static int rvin_setup(struct rvin_dev *vin)
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{
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- u32 vnmc, dmr, dmr2, interrupts;
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+ u32 vnmc, dmr, dmr2, interrupts, lines;
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bool progressive = false, output_is_yuv = false, input_is_yuv = false;
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+ bool halfsize = false;
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switch (vin->format.field) {
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case V4L2_FIELD_TOP:
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@@ -628,12 +631,15 @@ static int rvin_setup(struct rvin_dev *vin)
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/* Use BT if video standard can be read and is 60 Hz format */
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if (!vin->info->use_mc && vin->std & V4L2_STD_525_60)
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vnmc = VNMC_IM_FULL | VNMC_FOC;
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+ halfsize = true;
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break;
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case V4L2_FIELD_INTERLACED_TB:
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vnmc = VNMC_IM_FULL;
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+ halfsize = true;
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break;
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case V4L2_FIELD_INTERLACED_BT:
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vnmc = VNMC_IM_FULL | VNMC_FOC;
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+ halfsize = true;
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break;
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case V4L2_FIELD_NONE:
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vnmc = VNMC_IM_ODD_EVEN;
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@@ -676,11 +682,15 @@ static int rvin_setup(struct rvin_dev *vin)
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break;
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}
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- /* Enable VSYNC Field Toogle mode after one VSYNC input */
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- if (vin->info->model == RCAR_GEN3)
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- dmr2 = VNDMR2_FTEV;
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- else
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+ if (vin->info->model == RCAR_GEN3) {
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+ /* Enable HSYNC Field Toggle mode after height HSYNC inputs. */
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+ lines = vin->format.height / (halfsize ? 2 : 1);
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+ dmr2 = VNDMR2_FTEH | VNDMR2_HLV(lines);
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+ vin_dbg(vin, "Field Toogle after %u lines\n", lines);
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+ } else {
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+ /* Enable VSYNC Field Toogle mode after one VSYNC input. */
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dmr2 = VNDMR2_FTEV | VNDMR2_VLV(1);
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+ }
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/* Hsync Signal Polarity Select */
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if (!(vin->mbus_cfg.flags & V4L2_MBUS_HSYNC_ACTIVE_LOW))
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