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@@ -54,7 +54,8 @@
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#define INTCSR_INBOX_FULL_INT 0x1000 /* enable inbox full interrupt */
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/* read, or write clear inbox full interrupt */
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#define INTCSR_INBOX_INTR_STATUS 0x20000
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-#define INTCSR_INTR_ASSERTED 0x800000 /* read only, interrupt asserted */
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+/* read only, interrupt asserted */
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+#define INTCSR_INTR_ASSERTED 0x800000
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/****************************************************************************/
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/* AMCC - PCI non-volatile ram command register (byte 3 of master control/status register) */
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