drm/amd/display: Support 64-bit Polaris11 5k VSR

- pass full asic_id info into bw_calc_init instead of only version enum
- 64-bit Polaris11 needs an extra microsecond of dmif_urgent_latency
- add helper to convert from asic_id.family to bw_calc version enum

Signed-off-by: Joshua Aberback <Joshua.Aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/calcs/bandwidth_calcs.c

@@ -27,11 +27,34 @@
 #include "bandwidth_calcs.h"
 #include "dc.h"
 #include "core_types.h"
+#include "dal_asic_id.h"
 
 /*******************************************************************************
  * Private Functions
  ******************************************************************************/
 
+static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asic_id)
+{
+	switch (asic_id.chip_family) {
+
+	case FAMILY_CZ:
+		if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev))
+			return BW_CALCS_VERSION_STONEY;
+		return BW_CALCS_VERSION_CARRIZO;
+
+	case FAMILY_VI:
+		if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev))
+			// || ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)
+			return BW_CALCS_VERSION_POLARIS10;
+		if (ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev))
+			return BW_CALCS_VERSION_POLARIS11;
+		return BW_CALCS_VERSION_INVALID;
+
+	default:
+		return BW_CALCS_VERSION_INVALID;
+	}
+}
+
 static void calculate_bandwidth(
 	const struct bw_calcs_dceip *dceip,
 	const struct bw_calcs_vbios *vbios,
@@ -1954,18 +1977,20 @@ static void calculate_bandwidth(
  ******************************************************************************/
 void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 	struct bw_calcs_vbios *bw_vbios,
-	enum bw_calcs_version version)
+	struct hw_asic_id asic_id)
 {
 	struct bw_calcs_dceip dceip = { 0 };
 	struct bw_calcs_vbios vbios = { 0 };
 
+	enum bw_calcs_version version = bw_calcs_version_from_asic_id(asic_id);
+
 	dceip.version = version;
 
 	switch (version) {
 	case BW_CALCS_VERSION_CARRIZO:
 		vbios.memory_type = bw_def_gddr5;
 		vbios.dram_channel_width_in_bits = 64;
-		vbios.number_of_dram_channels = 2;
+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
 		vbios.number_of_dram_banks = 8;
 		vbios.high_yclk = bw_int_to_fixed(1600);
 		vbios.mid_yclk = bw_int_to_fixed(1600);
@@ -2075,7 +2100,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 	case BW_CALCS_VERSION_POLARIS10:
 		vbios.memory_type = bw_def_gddr5;
 		vbios.dram_channel_width_in_bits = 32;
-		vbios.number_of_dram_channels = 8;
+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
 		vbios.number_of_dram_banks = 8;
 		vbios.high_yclk = bw_int_to_fixed(6000);
 		vbios.mid_yclk = bw_int_to_fixed(3200);
@@ -2185,7 +2210,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 	case BW_CALCS_VERSION_POLARIS11:
 		vbios.memory_type = bw_def_gddr5;
 		vbios.dram_channel_width_in_bits = 32;
-		vbios.number_of_dram_channels = 4;
+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
 		vbios.number_of_dram_banks = 8;
 		vbios.high_yclk = bw_int_to_fixed(6000);
 		vbios.mid_yclk = bw_int_to_fixed(3200);
@@ -2206,7 +2231,10 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 		vbios.high_voltage_max_phyclk = bw_int_to_fixed(810);
 		vbios.data_return_bus_width = bw_int_to_fixed(32);
 		vbios.trc = bw_int_to_fixed(48);
-		vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
+		if (vbios.number_of_dram_channels == 2) // 64-bit
+			vbios.dmifmc_urgent_latency = bw_int_to_fixed(4);
+		else
+			vbios.dmifmc_urgent_latency = bw_int_to_fixed(3);
 		vbios.stutter_self_refresh_exit_latency = bw_int_to_fixed(5);
 		vbios.stutter_self_refresh_entry_latency = bw_int_to_fixed(0);
 		vbios.nbp_state_change_latency = bw_int_to_fixed(45);
@@ -2295,7 +2323,7 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip,
 	case BW_CALCS_VERSION_STONEY:
 		vbios.memory_type = bw_def_gddr5;
 		vbios.dram_channel_width_in_bits = 64;
-		vbios.number_of_dram_channels = 1;
+		vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits;
 		vbios.number_of_dram_banks = 8;
 		vbios.high_yclk = bw_int_to_fixed(1866);
 		vbios.mid_yclk = bw_int_to_fixed(1866);

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

@@ -1349,10 +1349,7 @@ static bool construct(
 	if (!dce110_hw_sequencer_construct(dc))
 		goto res_create_fail;
 
-	if (ASIC_REV_IS_STONEY(ctx->asic_id.hw_internal_rev))
-		bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_STONEY);
-	else
-		bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_CARRIZO);
+	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
 
 	bw_calcs_data_update_from_pplib(dc);
 

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

@@ -1394,7 +1394,7 @@ static bool construct(
 	if (!dce112_hw_sequencer_construct(dc))
 		goto res_create_fail;
 
-	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, BW_CALCS_VERSION_POLARIS11);
+	bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id);
 
 	bw_calcs_data_update_from_pplib(dc);
 

drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h

@@ -483,7 +483,7 @@ struct bw_calcs_output {
 void bw_calcs_init(
 	struct bw_calcs_dceip *bw_dceip,
 	struct bw_calcs_vbios *bw_vbios,
-	enum bw_calcs_version version);
+	struct hw_asic_id asic_id);
 
 /**
  * Return: