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@@ -272,6 +272,56 @@ static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
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},
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};
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+/*
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+ * 'gmac' class
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+ * cpsw/gmac sub system
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+ */
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+static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
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+ .rev_offs = 0x0,
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+ .sysc_offs = 0x8,
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+ .syss_offs = 0x4,
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+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
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+ SYSS_HAS_RESET_STATUS),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
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+ MSTANDBY_NO),
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+ .sysc_fields = &omap_hwmod_sysc_type3,
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+};
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+
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+static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
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+ .name = "gmac",
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+ .sysc = &dra7xx_gmac_sysc,
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+};
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+
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+static struct omap_hwmod dra7xx_gmac_hwmod = {
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+ .name = "gmac",
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+ .class = &dra7xx_gmac_hwmod_class,
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+ .clkdm_name = "gmac_clkdm",
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+ .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
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+ .main_clk = "dpll_gmac_ck",
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+ .mpu_rt_idx = 1,
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'mdio' class
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+ */
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+static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
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+ .name = "davinci_mdio",
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+};
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+
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+static struct omap_hwmod dra7xx_mdio_hwmod = {
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+ .name = "davinci_mdio",
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+ .class = &dra7xx_mdio_hwmod_class,
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+ .clkdm_name = "gmac_clkdm",
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+ .main_clk = "dpll_gmac_ck",
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+};
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+
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/*
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* 'dcan' class
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*
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@@ -343,19 +393,10 @@ static struct omap_dma_dev_attr dma_dev_attr = {
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};
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/* dma_system */
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-static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
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- { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
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- { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
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- { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
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- { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
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- { .irq = -1 }
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-};
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-
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static struct omap_hwmod dra7xx_dma_system_hwmod = {
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.name = "dma_system",
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.class = &dra7xx_dma_hwmod_class,
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.clkdm_name = "dma_clkdm",
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- .mpu_irqs = dra7xx_dma_system_irqs,
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.main_clk = "l3_iclk_div",
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.prcm = {
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.omap4 = {
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@@ -938,6 +979,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
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.dev_attr = &i2c_dev_attr,
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};
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+/*
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+ * 'mailbox' class
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+ *
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+ */
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+
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+static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
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+ .rev_offs = 0x0000,
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+ .sysc_offs = 0x0010,
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+ .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
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+ SYSC_HAS_SOFTRESET),
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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+ .sysc_fields = &omap_hwmod_sysc_type2,
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+};
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+
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+static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
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+ .name = "mailbox",
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+ .sysc = &dra7xx_mailbox_sysc,
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+};
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+
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+/* mailbox1 */
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+static struct omap_hwmod dra7xx_mailbox1_hwmod = {
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+ .name = "mailbox1",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox2 */
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+static struct omap_hwmod dra7xx_mailbox2_hwmod = {
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+ .name = "mailbox2",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox3 */
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+static struct omap_hwmod dra7xx_mailbox3_hwmod = {
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+ .name = "mailbox3",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox4 */
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+static struct omap_hwmod dra7xx_mailbox4_hwmod = {
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+ .name = "mailbox4",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox5 */
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+static struct omap_hwmod dra7xx_mailbox5_hwmod = {
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+ .name = "mailbox5",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox6 */
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+static struct omap_hwmod dra7xx_mailbox6_hwmod = {
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+ .name = "mailbox6",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox7 */
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+static struct omap_hwmod dra7xx_mailbox7_hwmod = {
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+ .name = "mailbox7",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox8 */
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+static struct omap_hwmod dra7xx_mailbox8_hwmod = {
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+ .name = "mailbox8",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox9 */
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+static struct omap_hwmod dra7xx_mailbox9_hwmod = {
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+ .name = "mailbox9",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox10 */
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+static struct omap_hwmod dra7xx_mailbox10_hwmod = {
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+ .name = "mailbox10",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox11 */
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+static struct omap_hwmod dra7xx_mailbox11_hwmod = {
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+ .name = "mailbox11",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox12 */
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+static struct omap_hwmod dra7xx_mailbox12_hwmod = {
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+ .name = "mailbox12",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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+/* mailbox13 */
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+static struct omap_hwmod dra7xx_mailbox13_hwmod = {
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+ .name = "mailbox13",
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+ .class = &dra7xx_mailbox_hwmod_class,
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+ .clkdm_name = "l4cfg_clkdm",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
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+ },
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+ },
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+};
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+
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/*
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* 'mcspi' class
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*
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@@ -1215,6 +1444,97 @@ static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
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},
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};
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+/* ocp2scp3 */
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+static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
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+ .name = "ocp2scp3",
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+ .class = &dra7xx_ocp2scp_hwmod_class,
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+ .clkdm_name = "l3init_clkdm",
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+ .main_clk = "l4_root_clk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_HWCTRL,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'PCIE' class
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+ *
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+ */
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+
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+static struct omap_hwmod_class dra7xx_pcie_hwmod_class = {
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+ .name = "pcie",
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+};
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+
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+/* pcie1 */
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+static struct omap_hwmod dra7xx_pcie1_hwmod = {
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+ .name = "pcie1",
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+ .class = &dra7xx_pcie_hwmod_class,
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+ .clkdm_name = "pcie_clkdm",
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+ .main_clk = "l4_root_clk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/* pcie2 */
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+static struct omap_hwmod dra7xx_pcie2_hwmod = {
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+ .name = "pcie2",
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+ .class = &dra7xx_pcie_hwmod_class,
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+ .clkdm_name = "pcie_clkdm",
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+ .main_clk = "l4_root_clk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/*
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+ * 'PCIE PHY' class
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+ *
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+ */
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+
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+static struct omap_hwmod_class dra7xx_pcie_phy_hwmod_class = {
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+ .name = "pcie-phy",
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+};
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+
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+/* pcie1 phy */
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+static struct omap_hwmod dra7xx_pcie1_phy_hwmod = {
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+ .name = "pcie1-phy",
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+ .class = &dra7xx_pcie_phy_hwmod_class,
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+ .clkdm_name = "l3init_clkdm",
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+ .main_clk = "l4_root_clk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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+/* pcie2 phy */
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+static struct omap_hwmod dra7xx_pcie2_phy_hwmod = {
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+ .name = "pcie2-phy",
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+ .class = &dra7xx_pcie_phy_hwmod_class,
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+ .clkdm_name = "l3init_clkdm",
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+ .main_clk = "l4_root_clk_div",
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+ .prcm = {
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+ .omap4 = {
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+ .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
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+ .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
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+ .modulemode = MODULEMODE_SWCTRL,
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+ },
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+ },
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+};
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+
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/*
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* 'qspi' class
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*
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@@ -1248,6 +1568,38 @@ static struct omap_hwmod dra7xx_qspi_hwmod = {
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},
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};
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+/*
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+ * 'rtcss' class
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+ *
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+ */
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+static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
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+ .sysc_offs = 0x0078,
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+ .sysc_flags = SYSC_HAS_SIDLEMODE,
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+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
|
|
|
+ SIDLE_SMART_WKUP),
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type3,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
|
|
|
+ .name = "rtcss",
|
|
|
+ .sysc = &dra7xx_rtcss_sysc,
|
|
|
+};
|
|
|
+
|
|
|
+/* rtcss */
|
|
|
+static struct omap_hwmod dra7xx_rtcss_hwmod = {
|
|
|
+ .name = "rtcss",
|
|
|
+ .class = &dra7xx_rtcss_hwmod_class,
|
|
|
+ .clkdm_name = "rtc_clkdm",
|
|
|
+ .main_clk = "sys_32k_ck",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
|
|
|
+ .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
/*
|
|
|
* 'sata' class
|
|
|
*
|
|
|
@@ -2007,6 +2359,19 @@ static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
};
|
|
|
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
|
|
|
+ .master = &dra7xx_l4_per2_hwmod,
|
|
|
+ .slave = &dra7xx_gmac_hwmod,
|
|
|
+ .clk = "dpll_gmac_ck",
|
|
|
+ .user = OCP_USER_MPU,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
|
|
|
+ .master = &dra7xx_gmac_hwmod,
|
|
|
+ .slave = &dra7xx_mdio_hwmod,
|
|
|
+ .user = OCP_USER_MPU,
|
|
|
+};
|
|
|
+
|
|
|
/* l4_wkup -> dcan1 */
|
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
|
|
|
.master = &dra7xx_l4_wkup_hwmod,
|
|
|
@@ -2254,6 +2619,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
};
|
|
|
|
|
|
+/* l4_cfg -> mailbox1 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
|
|
|
+ .master = &dra7xx_l4_cfg_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox1_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox2 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox2_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox3 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox3_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox4 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox4_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox5 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox5_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox6 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox6_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox7 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox7_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox8 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox8_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox9 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox9_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox10 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox10_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox11 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox11_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox12 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox12_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_per3 -> mailbox13 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_mailbox13_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
/* l4_per1 -> mcspi1 */
|
|
|
static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
|
|
|
.master = &dra7xx_l4_per1_hwmod,
|
|
|
@@ -2334,6 +2803,62 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
};
|
|
|
|
|
|
+/* l4_cfg -> ocp2scp3 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
|
|
|
+ .master = &dra7xx_l4_cfg_hwmod,
|
|
|
+ .slave = &dra7xx_ocp2scp3_hwmod,
|
|
|
+ .clk = "l4_root_clk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l3_main_1 -> pcie1 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie1 = {
|
|
|
+ .master = &dra7xx_l3_main_1_hwmod,
|
|
|
+ .slave = &dra7xx_pcie1_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_cfg -> pcie1 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1 = {
|
|
|
+ .master = &dra7xx_l4_cfg_hwmod,
|
|
|
+ .slave = &dra7xx_pcie1_hwmod,
|
|
|
+ .clk = "l4_root_clk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l3_main_1 -> pcie2 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pcie2 = {
|
|
|
+ .master = &dra7xx_l3_main_1_hwmod,
|
|
|
+ .slave = &dra7xx_pcie2_hwmod,
|
|
|
+ .clk = "l3_iclk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_cfg -> pcie2 */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2 = {
|
|
|
+ .master = &dra7xx_l4_cfg_hwmod,
|
|
|
+ .slave = &dra7xx_pcie2_hwmod,
|
|
|
+ .clk = "l4_root_clk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_cfg -> pcie1 phy */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie1_phy = {
|
|
|
+ .master = &dra7xx_l4_cfg_hwmod,
|
|
|
+ .slave = &dra7xx_pcie1_phy_hwmod,
|
|
|
+ .clk = "l4_root_clk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
+/* l4_cfg -> pcie2 phy */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pcie2_phy = {
|
|
|
+ .master = &dra7xx_l4_cfg_hwmod,
|
|
|
+ .slave = &dra7xx_pcie2_phy_hwmod,
|
|
|
+ .clk = "l4_root_clk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
|
|
|
{
|
|
|
.pa_start = 0x4b300000,
|
|
|
@@ -2352,6 +2877,14 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
};
|
|
|
|
|
|
+/* l4_per3 -> rtcss */
|
|
|
+static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
|
|
|
+ .master = &dra7xx_l4_per3_hwmod,
|
|
|
+ .slave = &dra7xx_rtcss_hwmod,
|
|
|
+ .clk = "l4_root_clk_div",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
|
|
|
{
|
|
|
.name = "sysc",
|
|
|
@@ -2650,6 +3183,8 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|
|
&dra7xx_l4_wkup__ctrl_module_wkup,
|
|
|
&dra7xx_l4_wkup__dcan1,
|
|
|
&dra7xx_l4_per2__dcan2,
|
|
|
+ &dra7xx_l4_per2__cpgmac0,
|
|
|
+ &dra7xx_gmac__mdio,
|
|
|
&dra7xx_l4_cfg__dma_system,
|
|
|
&dra7xx_l3_main_1__dss,
|
|
|
&dra7xx_l3_main_1__dispc,
|
|
|
@@ -2670,6 +3205,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|
|
&dra7xx_l4_per1__i2c3,
|
|
|
&dra7xx_l4_per1__i2c4,
|
|
|
&dra7xx_l4_per1__i2c5,
|
|
|
+ &dra7xx_l4_cfg__mailbox1,
|
|
|
+ &dra7xx_l4_per3__mailbox2,
|
|
|
+ &dra7xx_l4_per3__mailbox3,
|
|
|
+ &dra7xx_l4_per3__mailbox4,
|
|
|
+ &dra7xx_l4_per3__mailbox5,
|
|
|
+ &dra7xx_l4_per3__mailbox6,
|
|
|
+ &dra7xx_l4_per3__mailbox7,
|
|
|
+ &dra7xx_l4_per3__mailbox8,
|
|
|
+ &dra7xx_l4_per3__mailbox9,
|
|
|
+ &dra7xx_l4_per3__mailbox10,
|
|
|
+ &dra7xx_l4_per3__mailbox11,
|
|
|
+ &dra7xx_l4_per3__mailbox12,
|
|
|
+ &dra7xx_l4_per3__mailbox13,
|
|
|
&dra7xx_l4_per1__mcspi1,
|
|
|
&dra7xx_l4_per1__mcspi2,
|
|
|
&dra7xx_l4_per1__mcspi3,
|
|
|
@@ -2680,7 +3228,15 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
|
|
|
&dra7xx_l4_per1__mmc4,
|
|
|
&dra7xx_l4_cfg__mpu,
|
|
|
&dra7xx_l4_cfg__ocp2scp1,
|
|
|
+ &dra7xx_l4_cfg__ocp2scp3,
|
|
|
+ &dra7xx_l3_main_1__pcie1,
|
|
|
+ &dra7xx_l4_cfg__pcie1,
|
|
|
+ &dra7xx_l3_main_1__pcie2,
|
|
|
+ &dra7xx_l4_cfg__pcie2,
|
|
|
+ &dra7xx_l4_cfg__pcie1_phy,
|
|
|
+ &dra7xx_l4_cfg__pcie2_phy,
|
|
|
&dra7xx_l3_main_1__qspi,
|
|
|
+ &dra7xx_l4_per3__rtcss,
|
|
|
&dra7xx_l4_cfg__sata,
|
|
|
&dra7xx_l4_cfg__smartreflex_core,
|
|
|
&dra7xx_l4_cfg__smartreflex_mpu,
|
Arnd Bergmann