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@@ -543,6 +543,9 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
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/* trigger the LUT now */
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seqid = fsl_qspi_get_seqid(q, cmd);
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+ if (seqid < 0)
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+ return seqid;
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+
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qspi_writel(q, (seqid << QUADSPI_IPCR_SEQID_SHIFT) | len,
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base + QUADSPI_IPCR);
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@@ -671,7 +674,7 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
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* causes the controller to clear the buffer, and use the sequence pointed
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* by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
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*/
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-static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
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+static int fsl_qspi_init_ahb_read(struct fsl_qspi *q)
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{
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void __iomem *base = q->iobase;
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int seqid;
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@@ -696,8 +699,13 @@ static void fsl_qspi_init_ahb_read(struct fsl_qspi *q)
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/* Set the default lut sequence for AHB Read. */
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seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
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+ if (seqid < 0)
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+ return seqid;
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+
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qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
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q->iobase + QUADSPI_BFGENCR);
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+
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+ return 0;
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}
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/* This function was used to prepare and enable QSPI clock */
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@@ -805,9 +813,7 @@ static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
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fsl_qspi_init_lut(q);
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/* Init for AHB read */
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- fsl_qspi_init_ahb_read(q);
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-
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- return 0;
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+ return fsl_qspi_init_ahb_read(q);
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}
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static const struct of_device_id fsl_qspi_dt_ids[] = {
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